데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

Silicon Photonic Subsystems for Inter-Chip Optical Networks

The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment. The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity. The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes. The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes. To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s

Power and spectrally efficient integrated high-speed LED drivers for visible light communication

Recent trends in mobile broadband indicates that the available radio frequency (RF) spectrum will not be enough to support the data requirements of the immediate future. Visible light communication, which uses visible spectrum to transmit wirelessly could be a potential solution to the RF ’Spectrum Crunch’. Thus there is growing interest all over the world in this domain with support from both academia and industry. Visible light communication( VLC) systems make use of light emitting diodes (LEDs), which are semiconductor light sources to transmit information. A number of demonstrators at different data capacity and link distances has been reported in this area. One of the key problems holding this technology from taking off is the unavailability of power efficient, miniature LED drive schemes. Reported demonstrators, mostly using either off the shelf components or arbitrary waveform generators (AWGs) to drive the LEDs have only started to address this problem by adopting integrated drivers designed for driving lighting installations for communications. The voltage regulator based drive schemes provide high power efficiency (> 90 %) but it is difficult to realise the fast switching required to achieve the Mbps or Gbps data rates needed for modern wireless communication devices. In this work, we are exploiting CMOS technology to realise an integrated LED driver for VLC. Instead of using conventional drive schemes (digital to analogue converter (DAC) + power amplifier or voltage regulators), we realised a current steering DAC based LED driver operating at high currents and sampling rates whilst maintaining power efficiency. Compared to a commercial AWG or discrete LED driver, circuit realised utilisng complementary metal oxide semiconductor (CMOS) technology has resulted in area reduction (29mm2). We realised for the first time a multi-channel CMOS LED driver capable of operating up to a 500 MHz sample rate at an output current of 255 mA per channel and >70% power efficiency. We were able to demonstrate the flexibility of the driver by employing it to realise VLC links using micro LEDs and commercial LEDs. Data rates up to 1 Gbps were achieved using this system employing a multiple input, multiple output (MIMO) scheme. We also demonstrated the wavelength division multiplexing ability of the driver using a red/green/blue commercial LED. The first integrated digital to light converter (DLC), where depending on the input code, a proportional number of LEDs are turned ON, realising a data converter in the optical domain, is also an output from this research. In addition, we propose a differential optical drive scheme where two output branches of a current DAC are used to drive two LEDs achieving higher link performance and power efficiency compared to single LED drive

Circuit architectures for high speed CMOS clock and data recovery circuits

As semiconductor process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things (IOT), the availability of low-cost, low-power, high-speed and robust communication interfaces between these devices will be a major challenge that needs to be addressed. Even in traditional desktop computing devices, the off-chip bandwidth does not scale as fast as the on-chip bandwidth and has therefore been an important bottleneck to the growth in processing speed. Thus, intelligent techniques will have to be developed that allow the traditional lossy channels to be deployed at higher data rates, while minimizing cost and power, without paying much of a performance penalty. Over the last decade and a half, a great amount of research has been done to design monolithic transmitter and receiver integrated circuits (ICs) in silicon complementary metal-oxide semiconductor (CMOS) technology as opposed to traditional discrete SiGe, InP technologies owing to the low cost and ease of integration of CMOS technology. A key component of the receiver is the clock and data recovery (CDR) circuit, which extracts the clock from the incoming data stream and samples the data. The performance of the CDR is a major impediment to increasing data rates in a serial communication system. Several CDR architectures have been proposed to ensure that the performance is comparable to traditional discrete SiGe, InP devices. In this thesis, three different CDR circuit architectures are designed in a 180 nm CMOS process with a target data rate of 2 Gbps and compared in terms of performance, power and area. In order to provide a fair comparison, the corresponding channel and transmitter blocks are also designed and the entire serial communication link is simulated. The fundamentals of CDR circuit design are introduced and a complete guide to analysis and design of CDR circuits for high speed serial links is presented. The results of the comparison help to evaluate power, performance and area trade-offs during the design phase and to choose the right architecture for a given application

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity

Design of CMOS integrated phase-locked loops for multi-gigabits serial data links

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 üm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 üm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 üm CMOS technology

On-detector electronics for high speed data transport, control and power distribution for the LHCb VELO and ATLAS Pixel Upgrades

The Large Hadron Collider (LHC) will see an upgrade to higher luminosity to widen the scope of study of particle physics and this will be a major upgrade of the LHC. The LHC collides protons at an energy of 13 TeV in order to study the fundamental components of matter and the forces that bind them together. The High-Luminosity Large Hadron Collider (HL-LHC) will enter service after 2025, increasing the volume of the data for analysis by a factor of 10. The phenomena that physicists are looking for have a very low probability of occurring and this is why a very large amount of data is needed to detect them. Vertexing and tracking sub-detectors for these High Energy Physics (HEP) experiments deliver very high data rates that require multi-gigabit transmission links. Commercial solutions such as optical transmission or wire cabling are investigated, however, due to high radiation environments and low radiation length requirements, electrical transmission with low mass custom designs have to be considered. Designing transmission lines with this requirement does pose a challenge and optical data transmission is used when space and radiation limits allow. The increase in luminosity will produce more data making it possible to study the phenomena in more detail by increasing the number of collisions by a factor of between five and seven. The increase in data will require an enhanced readout system and related electronics to be able to transmit and read out the data for further processing. At the same time powering systems need to be looked at to understand cost effcient and reliable techniques to be able to power such electronics. The thesis focuses on the readout electronics of the LHCb Vertex Locator (known as the 'VELO') Upgrade and the ATLAS Inner Tracker (known as the 'ITk') Upgrade including design of some components of the sub-systems, testing for high-speed data signaling, powering schemes and analysis of PCB designs and scope for improvements. An introduction to the LHC and the four experiments that use its beam - ATLAS, CMS, ALICE and LHCb is outlined. The thesis work is focused on two of these detectors namely ATLAS (A Toroidal LHC ApparatuS) and LHCb (Large Hadron Collider beauty) and these are further explained and details of the sub-systems that make up these detectors are elaborated. Major differences to the upgrade of the experiments is explained highlighting the changes and the main challenges that would need to be addressed. The work on the On-detector electronics of the LHCb VELO Upgrade with details of the design requirements and implementations for the different components is described and test results are presented. Data tapes for carrying high speed data signals and control signals from the front-end chip to the Vacuum Feedthoough (VF) were designed and successfully tested to have a loss of < 10 dB at the Nyquist frequency of 2.5 GHz and a characteristic impedance of approximately 94 Ω which is within the 10% tolerance of 100 Ω for differential signals. Sensitivity to radiation damage as well as additional mass in the detector acceptance were some factors that motivated the design of the Opto Power board (OPB). In addition, there was a need to power the front-end ASICs but from outside the vacuum tank. The OPB was designed to meet these requirements in addition to be more easily accessible for repair and maintenance. The OPB is realised in an 8-layer stackup, with custom designed radiation hard ICs, and was designed for optical to electrical conversion of 20 high-speed data links at 5.12 Gb/s per link to be read by the Off-detector electronics. The board comprises 13 DC-DC converters for powering 12 ASICs, two front-end hybrids and the OPB itself with a total current supply of 26 A. The ATLAS experiment will implement the Inner Tracker (ITk) which is a new tracker to be installed during the major ATLAS Upgrade during Long Shutdown 3. The work on the ATLAS ITK addresses two topics; a novel pixel powering scheme adopting layout techniques for high-speed design. A serial powering scheme was evaluated to be an optimal option and this scheme was tested to understand its scope and implementation in the pixel endcap design and results are presented. A study to understand the existing Crescent Tape PCB layout and techniques to improve the design for high-speed data transmission was evaluated. Methods for analysing high-speed data using S-parameters and eye diagrams, sources of signal degradation and mitigation techniques, are detailed. The laboratory test setup for high-speed measurements with the equipments used is also explained

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

All-Silicon-Based Photonic Quantum Random Number Generators

Random numbers are fundamental elements in different fields of science and technology such as computer simulation like Monte Carlo-method simulation, statistical sampling, cryptography, games and gambling, and other areas where unpredictable results are necessary. Random number generators (RNG) are generally classified as “pseudo”-random number generators (PRNG) and "truly" random number generators (TRNG). Pseudo random numbers are generated by computer algorithms with a (random) seed and a specific formula. The random numbers produced in this way (with a small degree of unpredictability) are good enough for some applications such as computer simulation. However, for some other applications like cryptography they are not completely reliable. When the seed is revealed, the entire sequence of numbers can be produced. The periodicity is also an undesirable property of PRNGs that can be disregarded for most practical purposes if the sequence recurs after a very long period. However, the predictability still remains a tremendous disadvantage of this type of generators. Truly random numbers, on the other hand, can be generated through physical sources of randomness like flipping a coin. However, the approaches exploiting classical motion and classical physics to generate random numbers possess a deterministic nature that is transferred to the generated random numbers. The best solution is to benefit from the assets of indeterminacy and randomness in quantum physics. Based on the quantum theory, the properties of a particle cannot be determined with arbitrary precision until a measurement is carried out. The result of a measurement, therefore, remains unpredictable and random. Optical phenomena including photons as the quanta of light have various random, non-deterministic properties. These properties include the polarization of the photons, the exact number of photons impinging a detector and the photon arrival times. Such intrinsically random properties can be exploited to generate truly random numbers. Silicon (Si) is considered as an interesting material in integrated optics. Microelectronic chips made from Si are cheap and easy to mass-fabricate, and can be densely integrated. Si integrated optical chips, that can generate, modulate, process and detect light signals, exploit the benefits of Si while also being fully compatible with electronic. Since many electronic components can be integrated into a single chip, Si is an ideal candidate for the production of small, powerful devices. By complementary metal-oxide-semiconductor (CMOS) technology, the fabrication of compact and mass manufacturable devices with integrated components on the Si platform is achievable. In this thesis we aim to model, study and fabricate a compact photonic quantum random number generator (QRNG) on the Si platform that is able to generate high quality, "truly" random numbers. The proposed QRNG is based on a Si light source (LED) coupled with a Si single photon avalanche diode (SPAD) or an array of SPADs which is called Si photomultiplier (SiPM). Various implementations of QRNG have been developed reaching an ultimate geometry where both the source and the SPAD are integrated on the same chip and fabricated by the same process. This activity was performed within the project SiQuro—on Si chip quantum optics for quantum computing and secure communications—which aims to bring the quantum world into integrated photonics. By using the same successful paradigm of microelectronics—the study and design of very small electronic devices typically made from semiconductor materials—, the vision is to have low cost and mass manufacturable integrated quantum photonic circuits for a variety of different applications in quantum computing, measure, sensing, secure communications and services. The Si platform permits, in a natural way, the integration of quantum photonics with electronics. Two methodologies are presented to generate random numbers: one is based on photon counting measurements and another one is based on photon arrival time measurements. The latter is robust, masks all the drawbacks of afterpulsing, dead time and jitter of the Si SPAD and is effectively insensitive to ageing of the LED and to its emission drifts related to temperature variations. The raw data pass all the statistical tests in national institute of standards and technology (NIST) tests suite and TestU01 Alphabit battery without a post processing algorithm. The maximum demonstrated bit rate is 1.68 Mbps with the efficiency of 4-bits per detected photon. In order to realize a small, portable QRNG, we have produced a compact configuration consisting of a Si nanocrystals (Si-NCs) LED and a SiPM. All the statistical test in the NIST tests suite pass for the raw data with the maximum bit rate of 0.5 Mbps. We also prepared and studied a compact chip consisting of a Si-NCs LED and an array of detectors. An integrated chip, composed of Si p+/n junction working in avalanche region and a Si SPAD, was produced as well. High quality random numbers are produced through our robust methodology at the highest speed of 100 kcps. Integration of the source of entropy and the detector on a single chip is an efficient way to produce a compact RNG. A small RNG is an essential element to guarantee the security of our everyday life. It can be readily implemented into electronic devices for data encryption. The idea of "utmost security" would no longer be limited to particular organs owning sensitive information. It would be accessible to every one in everyday life