The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes

A new resonant circuit for 2.45 GHz LC VCO with linear frequency tuning

A new MOS varactor bank is proposed to implement a 2.45 GHz SiGe BiCMOS LC-tank voltage controlled oscillator (VCO) with linear frequency tuning. Compared to a conventional VCO, the proposed technique improves the quality factor of the LC-tank while preserving the linearity of the circuit. Realized in 0.25-μm SiGe BiCMOS technology, VCO exhibits 35% VCO gain (KVCO) variation from 2.29 to 2.66 GHz with a 16% tuning ratio. The VCO also exhibits a phase noise of -113 dBc/Hz at 1 MHz offset frequency and consumes 1.7 mA from 1.8 V supply

A tunable X-band SiGe HBT single stage cascode LNA

This paper presents an X-band silicon-germanium (SiGe) single stage cascode tunable low-noise amplifier (LNA) for active phased array transmit/receive modules. LNA is implemented by using IHP SiGe heterojunction bipolar transistors (HBTs) 0.25-μm SGB25V technology. Cadence is used in collaboration with ADS during schematic and layout design and the results depict that designed LNA dissipates 15.36 mW from an 2.4 V DC power supply and the maximum gain around 18 dB in X-band while not exceeding the 2.4 dB noise figure (NF). Reverse gain of the LNA is very low (<-40 dB). Input terminal is matched so that S11 is below -10 dB in X-band

A SiGe HEMT Mixer IC with Low Conversion Loss

The authors present the first SiGe HEMT mixer integrated circuit. The active mixer stage, operating up to 10GHz RF, has been designed and realized using a 0.1µ µµ µm gate length transistor technology. The design is based on a new large-signal simulation model developed for the SiGe HEMT. Good agreement between simulation and measurement is reached. The mixer exhibits 4.0dB and 4.7dB conversion loss when down-converting 3.0GHz and 6.0GHz signals, respectively, to an intermediate frequency of 500MHz using high-side injection of 5dBm local oscillator power. Conversion loss is less than 8dB for RF frequencies up to 10GHz with a mixer linearity of –8.8dBm input related 1dB compression point

100ps time resolution with thin silicon pixel detectors and a SiGe HBT amplifier

A 100um thick silicon detector with 1mm2 pad readout optimized for sub-nanosecond time resolution has been developed and tested. Coupled to a purposely developed amplifier based on SiGe HBT technology, this detector was characterized at the H8 beam line at the CERN SPS. An excellent time resolution of (106+-1)ps for silicon detectors was measured with minimum ionizing particles

Experimental study of thermal conductivity reduction of silicon-germanium nanocomposite for thermoelastic application

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2005.Includes bibliographical references (p. 67-70).To improve the thermoelectric energy conversion efficiency of silicon germanium (SiGe), two methods were used to decrease the thermal conductivity by increasing phonon boundary scattering at interfaces. In the first method, SiGe alloys were annealed at a temperature higher than the melting point to increase the number of grain boundaries. In the second method, SiGe composites were made with nanosize silicon particles. For annealed SiGe alloys thermal conductivity decreased by a factor of two while power factor remained the same value. For SiGe nanocomposite thermal conductivity decreased by a factor of four to that of bulk alloy, but electrical conductivity deteriorated. Future work will focus on increasing electrical conductivity while reducing the thermal conductivity.by Hohyun Lee.S.M

High-hole mobility Si1-xGex (0.1 ≤ x ≤ 1) on an insulator formed by advanced solid-phase crystallization

The grain size and hole mobility of polycrystalline Si1-xGex thin films formed on glass by solid-phase crystallization were significantly improved after preparing the amorphous precursors by heating the substrate. By just controlling the deposition temperature of the precursors (50–350 °C) for each SiGe composition, the grain size reached over 2 μm across the whole composition range. Reflecting the enlargement of the grain size, the hole mobility values were improved by approximately one order of magnitude. These values are comparable to those of single-crystal SiGe formed by Ge condensation and are the highest among SiGe on insulators synthesized at low temperature (<900 °C). The SiGe on insulator technology obtained in this study will greatly contribute to the development of SiGe-based electronic and optical devices

Computer Simulation and Device Physics of SiGe Heterojunction Bipolar Transistors

Recent advances in semiconductor growth technology have enabled the growth of SiGe strained layers on silicon substrates. Si/SiGe technology has a promising future, especially in microwave HBT applications. This work describes the development of an existing two-dimensional drift-diffusion device simulation program for accurate modelling of SiGe heterojunction bipolar transistors (HBT\u27s). PUPHS2D (Purdue University Program for Heterostructure Simulation in Two Dimensions) was formulated by Paul Dodd [Dod89] as an AlGaAs/GaAs HBT simulation tool. This work describes the extension of this program to the silicon and Si 1|_xGex material systems. The computer model allows the user to explore internal device physics as well as terminal characteristics of a device. Field-dependent mobility has been added to the program in order to more accurately compute high-field transport phenomena. The simulation tool is used to study the performance of silicon bipolar transistors and Si/SiGe HBT\u27s, and these results are presented in chapter 4