Analysis & experimental evaluation of single point moored buoy systems

Originally issued as Reference No. 69-36, series later renamed WHOI-This report reviews the analysis and the evaluation of surface buoy systems performed in the Engineering Department of the Woods Hole Oceanographic Institution in 1968. The buoy systems considered are single point moored, taut and compound consisting of wire and synthetic ropes, The first part of the report describes the forcing functions and the system response as measured in situ during and after launching, The second part presents the results of the mooring line components testing and evaluation programs performed at sea or in laboratories. The third part briefly outlines the present development in telemetry transmission of scientific and engineering information, It is believed that this systematic engineering effort is an important factor in the continuous improvement of the reliability and performance of the deep sea buoy systems used in scientific measurements programs.Submitted to the Office of Naval Research under Contract N00014-66-C0241, NR 083-00

Arbitration-Induced Preemption Delays

The interactions among concurrent tasks pose a challenge in the design of real-time multi-core systems, where blocking delays that tasks may experience while accessing shared memory have to be taken into consideration. Various memory arbitration schemes have been devised that address these issues, by providing trade-offs between predictability, average-case performance, and analyzability. Time-Division Multiplexing (TDM) is a well-known arbitration scheme due to its simplicity and analyzability. However, it suffers from low resource utilization due to its non-work-conserving nature. We proposed in our recent work dynamic schemes based on TDM, showing work-conserving behavior in practice, while retaining the guarantees of TDM. These approaches have only been evaluated in a restricted setting. Their applicability in a preemptive setting appears problematic, since they may induce long memory blocking times depending on execution history. These blocking delays may induce significant jitter and consequently increase the tasks\u27 response times. This work explores means to manage and, finally, bound these blocking delays. Three different schemes are explored and compared with regard to their analyzability, impact on response-time analysis, implementation complexity, and runtime behavior. Experiments show that the various approaches behave virtually identically at runtime. This allows to retain the approach combining low implementation complexity with analyzability

Duetto: Latency Guarantees at Minimal Performance Cost

The management of shared hardware resources in multi-core platforms has been characterized by a fundamental trade-off: high-performance arbiters typically employed in COTS systems offer no worst-case guarantees, while dedicated real-time controllers provide timing guarantees at the cost of significantly degrading system performance. In this paper, we overcome this trade-off by introducing Duetto, a novel hardware resource management paradigm. Duetto pairs a real-time arbiter with a high-performance arbiter and a latency estimator module. Based on the observation that the resource is rarely overloaded, Duetto executes the high-performance arbiter most of the time, switching to the real-time arbiter only in the rare cases when the latency estimator deems that timing guarantees risk being violated. We demonstrate our approach on the case study of a multi-bank memory. Our evaluation based on cycle-accurate simulations shows that Duetto can provide the same latency guarantees as the real-time arbiter with limited loss of performance compared to the high-performance arbiter

Fixed-Priority Memory-Centric Scheduler for COTS-Based Multiprocessors

Memory-centric scheduling attempts to guarantee temporal predictability on commercial-off-the-shelf (COTS) multiprocessor systems to exploit their high performance for real-time applications. Several solutions proposed in the real-time literature have hardware requirements that are not easily satisfied by modern COTS platforms, like hardware support for strict memory partitioning or the presence of scratchpads. However, even without said hardware support, it is possible to design an efficient memory-centric scheduler. In this article, we design, implement, and analyze a memory-centric scheduler for deterministic memory management on COTS multiprocessor platforms without any hardware support. Our approach uses fixed-priority scheduling and proposes a global "memory preemption" scheme to boost real-time schedulability. The proposed scheduling protocol is implemented in the Jailhouse hypervisor and Erika real-time kernel. Measurements of the scheduler overhead demonstrate the applicability of the proposed approach, and schedulability experiments show a 20% gain in terms of schedulability when compared to contention-based and static fair-share approaches

Microbiota Characterization of Poultry Processing Systems and Associated Microbiological Sampling Materials Collected at Commercial Processing Facilities

The poultry industry and associated regulatory bodies use whole bird carcass (WBC) rinsates to evaluate different stages of broiler processing systems for the prevalence of food-borne pathogens, including Salmonella spp. and Campylobacter spp. Within industry and research groups, the same sample collections are enumerated to determine E. coli, Enterobacteriaceae (EB), and Aerobic Plate Count (APC) microorganisms. Analysis of these indicator microorganisms provides numerical data that can be used to demonstrate the effects of specific process control steps where low occurrences of target pathogens hinder the exclusive use of prevalence data. With the utilization of next generation sequencing (NGS), including analysis of 16s rDNA sequences, a more complete characterization of the microbial communities present (the microbiota) can be identified. Microbiota analysis applied to samples collected within the pre-evisceration stages of a commercial broiler processing facility highlighted shifts in enteric microorganisms that were not fully recognized by traditional microbiological culture methods and provided a better understanding of cross-contamination events within those stages of the process. Additionally, microbiota data provided a more complete evaluation of spoilage and sanitary dress indicator microorganisms which were not identified using the traditional culturing methodologies. In addition to evaluating the processing system, microbiota analysis has also helped to identify how a change in the applied rinse solution could affect downstream microbiological analyses. Cultured microbiological methods indicated significant differences (P ≤ 0.05) in APC levels of the two rinsates, but no significant differences in EB, Salmonella spp. or Campylobacter spp. prevalence. In contrast, beta diversity analysis of the microbiota compositions of the two rinsate types and associated matrices used to assess those levels of microorganisms revealed a marked difference (P \u3c 0.05) at the operational taxonomic unit (OTU) level

DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance

© {Reza Mirosanlou, Mohamed Hassan, and Rodolfo Pellizzoni | ACM} {2021}. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in {In The International Symposium on Memory Systems }, https://doi.org/10.1145/3488423.3488431DRAM memory controllers (MCs) in COTS systems are designed primarily for average performance, offering no worst-case guarantees, while real-time MCs provide timing guarantees at the cost of a significant average performance degradation. For this reason, hardware vendors have been reluctant to integrate real-time solutions in high-performance platforms. In this paper, we overcome this performance-predictability trade-off by introducing DuoMC, a novel memory controller that promotes to augment COTS MCs with a real-time scheduler and run-time monitoring to provide predictability guarantees. Leveraging the fact that the resource is barely overloaded, DuoMC allows the system to enjoy the high performance of the conventional MC most of the time, while switching to the real-time scheduler only when timing guarantees risk being violated, which rarely occurs. In addition, unlike most existing real-time MCs, DuoMC enables the utilization of both private and shared DRAM banks among cores to facilitate communication among tasks. We evaluate DuoMC using a cycle-accurate multi-core simulator. Results show that DuoMC can provide better or comparable latency guarantees than state-of-the-art real-time MCs with limited performance loss (only 8% in the worst scenario) compared to the COTS MC

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

This survey provides an overview of the scientific literature on timing verification techniques for multi-core real-time systems. It reviews the key results in the field from its origins around 2006 to the latest research published up to the end of 2018. The survey highlights the key issues involved in providing guarantees of timing correctness for multi-core systems. A detailed review is provided covering four main categories: full integration, temporal isolation, integrating interference effects into schedulability analysis, and mapping and allocation. The survey concludes with a discussion of the advantages and disadvantages of these different approaches, identifying open issues, key challenges, and possible directions for future research

Defense Technical Information Center thesaurus

This DTIC Thesaurus provides a basic multidisciplinary subject term vocabulary used by DTIC to index and retrieve scientific and technical information from its various data bases and to aid DTIC`s users in their information storage and retrieval operations. It includes an alphabetical posting term display, a hierarchy display, and a Keywork Out of Context (KWOC) display

Program and abstracts

We are pleased that the program in 2022 will be more interesting than ever and it will include the following topics: Mathematical Modeling in Cancer Therapy, Gene Therapy, Archaeological Genetics, New perspectives in Human Forensic Molecular Biology, Genomics in Medicine, Pharmacogenomics and Drug Development, Stem Cells in Medicine, Regenerative Medicine, Ribosomes in Medicine, Epigenomics, Crime Scene Investigation, Forensic Genetics, and Mass Catastrophes Managements. This year, the third "Nobel Spirit" will provide a forum to the three Nobel laureates to stimulate public discussion on the role of science in solving global health issues, acute regional problems such as brain drain, demographic decline, as well as cultural and social change. In addition, we are organizing a very stimulating Session on Bioanthropology and global health in the times of crisis, as well as Joint Event ISABS and Ministry of the Interior - Crime Scene Investigation Training Course: Mystery on the ship —Investigation of the water-related crime scene

Timing Predictable and High-Performance Hardware Cache Coherence Mechanisms for Real-Time Multi-Core Platforms

Multi-core platforms are becoming primary compute platforms for real-time systems such as avionics and autonomous vehicles. This adoption is primarily driven by the increasing application demands deployed in real-time systems, and the cost and performance benefits of multi-core platforms. For real-time applications, satisfying safety properties in the form of timing predictability, is the paramount consideration. Providing such guarantees on safety properties requires applying some timing analysis on the application executing on the compute platform. The timing analysis computes an upper bound on the application’s execution time on the compute platform, which is referred to as the worst-case execution time (WCET). However, multi-core platforms pose challenges that complicate the timing analysis. Among these challenges are timing challenges caused due to simultaneous accesses from multiple cores to shared hardware resources such as shared caches, interconnects, and off-chip memories. Supporting timing predictable shared data communication between real-time applications further compounds this challenge as a core’s access to shared data is dependent on the simultaneous memory activity from other cores on the shared data. Although hardware cache coherence mechanisms are the primary high-performance data communication mechanisms in current multi-core platforms, there has been very little use of these mechanisms to support timing predictable shared data communication in real-time multi-core platforms. Rather, current state-of-the-art approaches to timing predictable shared data communication sidestep hardware cache coherence. These approaches enforce memory and execution constraints on the shared data to simplify the timing analysis at the expense of application performance. This thesis makes the case for timing predictable hardware cache coherence mechanisms as viable shared data communication mechanisms for real-time multi-core platforms. A key takeaway from the contributions in this thesis is that timing predictable hardware cache coherence mechanisms offer significant application performance over prior state-of-the-art data communication approaches while guaranteeing timing predictability. This thesis has three main contributions. First, this thesis shows how a hardware cache coherence mechanism can be designed to be timing predictable by defining design invariants that guarantee timing predictability. We apply these design invariants and design timing predictable variants of existing conventional cache coherence mechanisms. Evaluation of these timing predictable cache coherence mechanisms show that they provide significant application performance over state-of-the-art approaches while delivering timing predictability. Second, we observe that the large worst-case memory access latency under timing predictable hardware cache coherence mechanisms questions their applicability as a data communication mechanism in real-time multi-core platforms. To this end, we present a systematic framework to design better timing predictable cache coherence mechanisms that balance high application performance and low worst-case memory access latency. Our systematic framework concisely captures the design features of timing predictable cache coherence mechanisms that impacts their WCET, and identifies a spectrum of approaches to reduce the worst-case memory access latency. We describe one approach and show that this approach reduces the worst-case memory access latency of timing predictable cache coherence mechanisms to be the same as alternative approaches while trading away minimal performance in the original cache coherence mechanisms. Third, we design a timing predictable hardware cache coherence mechanism for multi-core platforms used in mixed-critical real-time systems (MCS). Applications in MCS have varying performance and timing predictability requirements. We design a timing predictable cache coherence mechanism that considers these differing requirements and ensures that applications with no timing predictability requirements do not impact applications with strict predictability requirements