Editorial: clock/frequency generation circuits and systems

1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2Department of Electronics, University of Pavia, 27100 Pavia, Italy 3Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea 4Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan 5Electrical Engineering Department, University of California, Los Angeles, CA 90095, US

Clock/Frequency Generation Circuits and Systems

1 Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2Department of Electronics, University of Pavia, 27100 Pavia, Italy 3Department of Electrical Engineering, Pohang University of Science and Technology, Kyungbuk 790-784, Republic of Korea 4Department of Physical Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan 5Electrical Engineering Department, University of California, Los Angeles, CA 90095, US

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 um CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gbps/channel and occupying a silicon area of 0.045 mm2/channel, with the total aggregate data bit rate of 20 Gbps. The measured FTOL is 3.5% and no error was detected for a 231-1 PRBS (pseudo-random bit stream) input data for 30 minutes meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning-range and compensated loop-gain has been applied to tune the center frequency of all CDR channels on desired frequency

Fractional-N DLL for clock synchronization

Master'sMASTER OF ENGINEERIN

LPDDR5의 외장 자가 테스트를 위한 고속 송신기의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.To overcome the speed gap between Automatic Test Equipment (ATE) and memory, the concept of Built-out Self-test (BOST) was introduced. This thesis presents the design of a transmitter for BOST of LPDDR5. It transmits high-speed DQS and WCK to DRAM while receiving low-speed clocks from ATE. Since they don’t always have clock-toggle, a digital block generates some data patterns. Also, by phase interpolators, phases of the outputs are shifted by desired. The analog part of the transmitter consists of phase interpolators, serializers, and drivers. Phase interpolators and drivers are designed in a current mode to be resistant to supply noise. The divider of the serializer is newly proposed so that the timings of all outputs are the same. In addition, the time it takes to receive enabling signals from ATE and transmit outputs to DRAM is constant. As a result, the transmitter sends DQS and WCK with data patterns to DRAM at the desired timing. The proposed transmitter is fabricated in a 40 nm CMOS process. 1 TX lane consumes 31.4 mW and occupies 0.06 mm2. Measured DQS has a swing of 230 mV and an RMS jitter of 770 fs at 10 Gb/s with 50 Ω termination. And WCK has a swing of 185 mV and an RMS jitter of 894 fs at 10 Gb/s with 40 Ω termination.자동 테스트 장비 (ATE)와 메모리 간의 속도 차이를 극복하기 위해 외장 자가 테스트 (BOST) 개념이 도입되었다. 본 논문은 LPDDR5의 BOST를 위한 송신기 설계를 제시한다. 송신기는 ATE에서 저속 클럭을 받아서 고속 DQS와 WCK를 DRAM에 전송한다. 출력에 항상 클럭 토글만 있는 것은 아니므로 데이터 패턴이 디지털 블록에서 생성된다. 또한 위상 보간기로 출력의 위상을 원하는 대로 움직인다. 송신기의 아날로그 부분은 위상 보간기, 시리얼라이저, 드라이버로 구성된다. 위상 보간기와 드라이버는 공급 노이즈에 견고하도록 전류 모드로 설계되었다. 시리얼라이저의 디바이더가 새롭게 제안되어서 모든 출력의 타이밍이 같다. 또한 ATE에서 활성화 신호를 받아서 DRAM으로 출력을 전송하는데 걸리는 시간도 일정하다. 그 결과 송신기는 데이터 패턴이 있는 DQS와 WCK를 원하는 타이밍에 DRAM으로 전송한다. 제안된 송신기는 40 nm CMOS 공정으로 제작되었다. 송신기의 하나의 레인은 31.4 mW를 소비하고 0.06mm2를 차지한다. 측정된 DQS는 50 Ω 터미네이션일 때 10 Gb/s에서 230 mV의 스윙과 770 fs의 RMS 지터를 가진다. 그리고 WCK는 40 Ω 터미네이션일 때 10 Gb/s에서 185 mV의 스윙과 894 fs의 RMS 지터를 갖는다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON SERIAL LINK 4 2.1 OVERVIEW 4 2.2 BASIS OF MEMORY INTERFACE 7 2.3 BUILDING BLOCKS 9 2.3.1 PHASE INTERPOLATOR 9 2.3.2 SERIALIZER 14 2.3.3 DRIVER 18 CHAPTER 3 DESIGN OF TRANSMITTER FOR BOST 22 3.1 DESIGN CONSIDERATION 22 3.2 OVERALL ARCHITECTURE 24 3.3 CIRCUIT IMPLEMENTATION 26 3.3.1 CLOCK PATH 26 3.3.2 PHASE INTERPOLATOR 29 3.3.3 SERIALIZER 33 3.3.4 DRIVER 41 CHAPTER 4 MEASUREMENTS RESULTS 48 4.1 DIE PHOTOMICROGRAPH 48 4.2 MEASUREMENT SETUP 49 4.3 MEASUREMENT RESULTS 51 4.4 PERFORMANCE SUMMARY 57 CHAPTER 5 CONCLUSION 59 BIBLIOGRAPHY 60 초 록 63석

A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully

Highly digital power efficient techniques for serial links

Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques

Strategies for enhancing DC gain and settling performance of amplifiers

The operational amplifier (op amp) is one of the most widely used and important building blocks in analog circuit design. High gain and high speed are two important properties of op amps because they determine the settling behavior of the op amps. As supply voltages decrease, the realization of high gain amplifiers with large Gain-Bandwidth-Products (GBW) has become challenging. The major focus in this dissertation is on the negative output impedance gain enhancement technique. The negative impedance gain enhancement technique offers potential for achieving very high gain and energy-efficient fast settling and is low-voltage compatible. Misconceptions that have limited the practical adoption of this gain enhancement technique are discussed. A new negative conductance gain enhancement technique was proposed. The proposed circuit generates a negative conductance with matching requirements for achieving very high DC gain that are less stringent than those for existing -g m gain enhancement schemes. The proposed circuit has potential for precise digital control of a very large DC gain. A prototype fully differential CMOS operational amplifier was designed and fabricated based on the proposed gain enhancement technique. Experimental results which showed a DC gain of 85dB and an output swing of 876mVp-p validated the fundamental performance characteristics of this technique. In a separate section, a new amplifier architecture with bandpass feedforward compensation is presented. It is shown that a bandpass feedforward path can be used to substantially extend the unity-gain-frequency of an operational amplifier. Simulation results predict significant improvements in rise time and settling performance and show that the bandpass compensation scheme is reasonably robust. In the final section, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0\u27s and 1\u27s in a data stream. This system does not require clock recovery, suffers no loss of data during acquisition, has a reduced sensitivity to jitter in the incoming data and does not exhibit jitter enhancement associated with VCO tracking in a PLL

Digital phase tightening for improved spatial resolution in millimeter-wave imaging systems

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Includes bibliographical references (leaves 68-69).Imaging systems using millimeter-wave frequencies allow for the possibilities of vehicular radar and concealed weapons detection. By using silicon technology, the integration of millimeter-wave circuits can reach new levels that were previously impossible. This thesis discusses the challenge and design of a mm-wave imaging system using a technique called digital phase tightening for improved spatial resolution. Digital phase tightening uses feedback and oversampling to accurately measure the amplitude and phase of an incoming signal. Furthermore, it can be implemented using only a delay-lock loop, an analog-to-digital converter, and a counter. A proof of concept system utilizing a 2.4GHz delay-lock loop with supporting circuitry is designed in 90nm CMOS. Test results demonstrate a proof of concept system with a measured DLL resolution of 41.7ps that consumes 36mW of power. The goal of the system is to reduce the jitter of phase measurements to the order of femto-seconds. In the proto system, the quantization error is larger than the Gaussian noise; therefore, significant improvements in the accuracy of the phase measurements were not observed.by Ke Lu.S.M