Design of VCOs in Deep Sub-micron Technologies

This work will present a more accurate frequency prediction model for single-ended ring oscillators (ROs), a case-study comparing different ROs, and a design method for LC voltage-controlled oscillators (LCVCOs) that uses a MATLAB script based on analytical equations to output a graphical design space showing performance characteristics as a function of design parameters. Using this method, design trade-offs become clear, and the designer can choose which performance characteristics to optimize. These methods were used to design various topologies of ring oscillators and LCVCOs in the GlobalFoundries 28 nm HPP CMOS technology, comparing the performance between different topologies based on simulation results. The results from the MATLAB design script were compared to simulation results as well to show the effectiveness of the design methods. Three varieties of 5 GHz voltage controlled ring oscillators were designed in the GlobalFoundries 28 nm HPP CMOS technology. The first is a low current low dropout regulator (LDO) tuned ring oscillator designed with thin oxide devices and a 0.85 V supply. The second is a high current LDO-tuned ring oscillator designed with medium oxide devices and a 1.5 V supply. The third is varactor-tuned ring oscillator with no LDO, and 0.85 V supply. Performance comparison of these ring oscillator systems are presented, outlining trade-offs between tuning range, phase noise, power dissipation, and area. The varactor-tuned ring oscillator exhibits 8.89 dBc/Hz (with power supply noise) and 16.27 dBc/Hz (without power supply noise) improvement in phase noise over the best-performing LDO-tuned ring oscillator. There are advantages in average power dissipation and area for a minimal tradeoff in tuning range with the varactor-tuned ring oscillator. Four multi-GHz LCVCOs were designed in the GlobalFoundries 28 nm HPP CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz varactor-tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only, and 8.2 GHz digitally-tuned self-biased CMOS. As a design method, analytical ex-pressions describing tuning range, tank amplitude constraint, and startup condition were used in MATLAB to output a graphical view of the design space for both NMOS-only and CMOS LCVCOs, with maximum varactor capacitance on the y-axis and NMOS transistor width on the x-axis. Phase noise was predicted as well. In addition to the standard varactor control voltage tuning method, digitally-tuned implementations of both NMOS and CMOS LCVCOs are presented. The performance aspects of all designed LCVCOs are compared. Both varactor-tuned and digitally-tuned NMOS LCVCOs have lower phase noise, lower power consumption, and higher tuning range than both CMOS topologies. The varactor-tuned NMOS LCVCO has the lowest phase noise of -97 dBc/Hz at 1 MHz offset from 15 GHz center frequency, FOM of -172.20 dBc/Hz, and FOMT of -167.76 dBc/Hz. The digitally-tuned CMOS LCVCO has the greatest tuning range at 10%. Phase noise is improved by 3 dBc/Hz with the digitally-tuned CMOS topology over varactor-tuned CMOS

Impedance model analysis and measurement for power system stability

Electric power systems are transforming from synchronous machine (SG) dominated systems to composite grids in which inverter-based resources (IBRs) coexist with SGs. The lack of standardisation of IBRs leads vendors to treat their control algorithms as commercial secrets and they are willing to disclose only black-box models that give input-output relationships but no internal details. An impedance model spectrum is commonly put forward as a black-box model useful for stability analysis. Several types of impedance models have been proposed to represent the dynamic characteristics of a complete power networks. A study is undertaken to compare two types of networked impedance models: those based on direct nodal or loop analysis and those based on a whole-system formulation. The underlying relationship between eigenvalues of the impedance matrix and the oscillatory modes of the network for both model types have been unclear but are resolved here and the relative merits of the models are established. Through examining eigenvalue sensitivity, a proposal is made for an impedance participation factor that can identify root-causes of low damping. It is proved that the impedance participation factor is related to the classic state-space participation via a chain-rule relationship. Based on the chain-rule, a grey-box approach is developed as a generic method for root-cause tracing in impedance models. It has three degrees of transparency according to the available information and they are aggregated participation, damping contribution, and key parameters. The grey-box approach can indicate appropriate re-tuning of parameters that would shift the oscillatory mode in a desired direction in complex plain so as to stabilise the system. The theoretical contributions are verified through three different scales of case study: a simple three-node passive circuit, a modified IEEE 14-bus system and a modified NETS-NYPS 68-bus system. A significant advantage of using an impedance model is that the model can, in principle, be measured online with injection of a small-signal perturbation. However, a vital issue of concern is error caused by noise in the measured signals since this will determine the magnitude of injected perturbation required and the practicality of arranging that. To address this issue, a noise analysis process for impedance measurement is proposed in this thesis, from which guidance on selecting an appropriate injection magnitude can be provided. To verify the proposed analysis process, a power-hardware-in-the-loop system is built where a high-bandwidth power amplifier (OP1400 series) is used to inject the perturbation. The theoretical developments and noise analysis presented in this thesis combine to offer stability analysis and root-cause tracing of the type normally found only in white box state-space models but here are available in models built from equipment manufacturers' black-box models or from measurement-based models.Open Acces

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Phase domain modelling and simulation of large-scale power systems with VSC-based FACTS equipment

Most of the analysis techniques available for planning and operation of multiphase power systems are based upon the assumption that the network operates under perfectly balanced conditions. The advantage of this assumption from the modelling view point is that only one phase of the three phase system needs to be considered for analysis, resulting in a reduced size of the problem at hand. However, the phase frame of reference offers a more general representation for the solution of power system problems than the frame of reference provided by the sequences. The former can accommodate networks containing any degree of unbalance whilst the latter is only applicable to power networks exhibiting perfect or near-perfect impedance balance between phases. The thesis reports on the development of steady state and time domain models of Flexible AC Transmission System (FACTS) controllers in the natural framework of electric systems, i.e. namely the phase co-ordinates domain. The FACTS equipment selected for analytical development in this research are: the static synchronous compensator (STATCOM), the static synchronous series compensator (SSSC), the unified power flow controller (UPFC) and the high-voltage direct current (HVDC). These power electronics-based controllers have the voltage source converter as their main constituent. The combined solution of both steady state and dynamic power flow equations pertaining to the VSC-based FACTS controllers and the power network are fully described in the thesis. The steady-state mathematical models of VSC-based FACTS controllers are formulated in nodal form using the frame of reference of the phases. Guidelines for their implementation into two distinct power flows algorithm namely, the Newton-Raphson in polar co-ordinates and the Newton-Raphson in rectangular coordinates are given. For the purpose of long-term dynamic assessment, a simultaneous solution using implicit trapezoidal integration method with Newton iteration is used to solve the set of differential-algebraic equations of generating plants and network components. In order to assess both the steady state and the dynamic behaviour of the models developed, a comprehensive, newly developed integrated software environment is used

Advanced Syncom, volume 1 Summary report

Synchronous communications satellite configuration, instrumentation, handling and test equipment, and systems desig

Coordinated Voltage Control in Modern Distribution Systems

Modern distribution systems, especially with the presence of distributed generation (DG) and distribution automation are evolving as smart distribution systems. Distribution management systems (DMSs) with communication infrastructure and associated software and hardware developments are integral parts of the smart distribution systems. With such advancement in distribution systems, distribution system voltage and reactive power control are dominant by Volt/VAr (voltage and reactive power) optimisation and utilisation of DG for system Volt/VAr support. It is to be noted that the respective controls and optimisation formulations are typically adopted from primary, secondary and tertiary voltage and reactive power controls at upstream system level. However, the characteristics of modern distribution systems embedded with high penetration of DG are different from transmission systems and the former distribution systems with uni-directional power flow. Also, coordinated control of multiple Volt/VAr support DG units with other voltage control devices such as on-load tap changer (OLTC), line voltage regulators (VRs) and capacitor banks (CBs) is one of the challenging tasks. It is mainly because reverse power flow, caused predominantly by DG units, can influence the operation of conventional voltage control devices. Some of the adverse effects include control interactions, operational conflicts, voltage drop and rise cases at different buses in a network, and oscillatory transients. This research project aimed to carry out in-depth study on coordinated voltage control in modern MV distribution systems utilising DG for system Volt/VAr support. In the initial phase of the research project, an in-depth literature review is conducted and the specific research gaps are identified. The design considerations of the proposed coordinated voltage control, which also uses the concept of virtual time delay, are identified through comprehensive investigations. It emphasises on examining and analysing both steady-state and dynamic phenomena associated with the control interactions among multiple Volt/VAr support DG units and voltage control devices. It would be essential for ensuring effective coordinated voltage control in modern distribution systems. In this thesis, the interactions among multiple DG units and voltage control devices are identified using their simultaneous and non-simultaneous responses for voltage control through time domain simulations. For this task, an analytical technique is proposed and small signal modelling studies have also been conducted. The proposed methodology could be beneficial to distribution network planners and operators to ensure seamless network operation from voltage control perspective with increasing penetration of DG units. Notably, it has been found that the significant interactions among multiple DG units and voltage control devices are possible under conventional standalone, rule-based, and analytics based control strategies as well as with real-time optimal control under certain system conditions. In the second phase of the research project, the proposed coordinated voltage control strategy is elaborated. The control design considerations are fundamentally based on eliminating the adverse effects, which can distinctly be caused by the simultaneous and non-simultaneous responses of multiple Volt/VAr support DG units and voltage control devices. First, the concept of virtual time delay is applied for dynamically managing the control variables of Volt/VAr support DG units and voltage control devices through the proposed control parameter tuning algorithm. Because it has been found that the conventional time-graded operation cannot eliminate the adverse effects of DG-voltage control device interactions under certain system conditions. Secondly, the distinct control strategies are designed and tested for effectively and efficiently coordinating the operation of multiple Volt/VAr support DG units and voltage control devices in real-time. The test results have demonstrated that the proposed coordinated voltage control strategy for modern MV distribution systems can effectively be implemented in real-time using advanced substation centred DMS. The proposed coordinated voltage control strategy presented in this thesis may trigger paradigm shift in the context of voltage control in smart distribution systems. In the final phase of the research project, short-term and/or long-term oscillations which can be possible for a MV distribution system operation embedded with Volt/VAr support DG are discussed. Typically, the short-term oscillations are occurred due to interactions among different DG units and their controllers (i.e., inter-unit electro-mechanical oscillations in synchronous machine based DG units) while the long-term oscillations occurred due to DG-voltage control device interactions. Also, sustained oscillations may occur due to tap changer limit cycle phenomenon. The concept of alert-state voltage control is introduced for mitigating the sustained oscillations subjected to OLTC limit cycles in the presence of high penetration of DG. The investigative studies in this thesis further emphasise the requirements of supplementary control and other mitigating strategies for damping the oscillations in modern active MV distribution systems. The proposed research will pave the way for managing increasing penetration of DG units, with different types, technologies and operational modes, from distribution system voltage control perspective