Pipeline-Based Power Reduction in FPGA Applications

This paper shows how temporal parallelism has an important role in the power dissipation reduction in the FPGA field. Glitches propagation is blocked by the flip-flops or registers in the pipeline. Several multiplication structures are implemented over modern FPGAs, StratixII and Virtex4, comparing their results with and without pipeline and hardware duplication

Low-Noise Energy-Efficient Sensor Interface Circuits

Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone. Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy. An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures. Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd

Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring

This paper describes a mixed-signal ECG system for personalized and remote cardiac health monitoring. The novelty of this work is four-fold. Firstly, a low power analog front end with an efficient automatic gain control mechanism, maintaining the input of the ADC to a level rendering optimum SNR and the enhanced recyclic folded cascode opamp used as an integrator for ADC. Secondly, a novel on-the-fly PQRST Boundary Detection (BD) methodology is formulated for finding the boundaries in continuous ECG signal. Thirdly, a novel low-complexity ECG feature extraction architecture is designed by reusing the same module present in the proposed BD methodology. Fourthly, the system is having the capability to reconfigure the proposed Low power ADC for low (8 bits) and high (12 bits) resolution with the use of the feedback signal obtained from the digital block when it is in processing. The proposed system has been tested and validated on patient’s data from PTBDB, CSEDB and in-house IIT Hyderabad DB (IITHDB) and we have achieved an accuracy of 99% upon testing on various normal and abnormal ECG signals. The whole system is implemented in 180 nm technology resulting in 9.47W (@ 1 MHz) power consumption and occupying 1.74mm2 silicon area

Programmable logic devices in sensor networks: a survey

This paper presents a survey about the use of reconfigurable hardware technologies in sensor networks, considering proposals published in two of the leading conferences of Programmable Logic Devices: FPL and SPL. These proposals cover different applications such as wireless communications, different networks topics and sensors. Some of the papers considered in this survey are directly related with WSN, such as reconfigurable nodes or lowpower hardware platforms intended for sensor networks. Other papers are not directly related to WSN, but they present results and concepts that may be of interest in the field of the WSNs.Sociedad Argentina de Informática e Investigación Operativ

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA

Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator\u27s frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.The 20th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2014), Nov 19-21, 2014, Singapor

A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors

Recent developments in reconfigurable multiprocessor system on chip (MPSoC) have offered system designers a great amount of flexibility to exploit task concurrency with higher throughput and less energy consumption. This paper presents a novel fuzzy logic reconfiguration engine (FLRE) for coarse grain MPSoC reconfiguration that facilitates to identify an optimum balance between power and performance of the system. The FLRE is composed on two levels of abstraction layers. The system selects an optimal configuration of Level 1 / Level 2 cache size and Associativity, processor operating frequency and voltage, the number of cores based on miss rate, and energy and throughput information of the system both at core and SoC level. An 8-core symmetric chip multiprocessor has been used to evaluate the proposed scheme. The results show an overall decrease of energy consumption with not more than 30% decrease in the throughput

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

In this paper, we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in CS CMOS image sensors are recursive pseudo-random binary matrices. We have proved that the restricted isometry property of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random number generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behavior that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber reconstruction algorithm. By means of single value decomposition, we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N000141410355European Union H2020 76586

Design and application of reconfigurable circuits and systems

Open Acces

System design and risk assessment for safety critical control software product lines

A methodology is presented for the design of safety critical product lines for control automation software. The functional failure identification and propagation risk assessment method is used in the early design phase of the mechatronic system. The applied methodology starts with the decomposition of the system into functions that are connected by energy, material and signal flows. This results in a functional model that does not make any assumptions on what components are used to realize the functions. The functions are mapped to mechatronic components in a model that can be simulated: the configuration flow graph. Functional failure logic is executed in parallel to the simulation to monitor the simulation signals and to determine the health of each function. The functional health results of the simulation, when critical events are injected, are used to identify the propagation of functional failures. Alternative designs that are described with a feature model, combinations of component parameter values and changes in the critical event scenario can be simulated. System designs that result in undesirable behavior are rejected. The purpose is to identify risks and to determine mechatronic designs with adequate safety characteristics before the design process branches into software, electrical and mechanical domains. The final deliverable of the mechatronic system design phase is a feature model capturing the design alternatives with acceptable safety characteristics. The aspect of this model containing software is the starting point for software product line engineering. In control automation, programmable logic controller targets are used, so a methodology and toolchain for supporting software product line configuration for such platforms has been developed using the PLCopen standard. Two case studies are used to demonstrate the methodology: a boiling water reactor, with a focus on reactor coolant pumps, and a mobile elevating work platform