Towards Neuro-Inspired Electronic Oscillators Based on The Dynamical Relaying Mechanism

Electronic oscillators are used for the generation of both continuous and discrete signals, playing a fundamental role in today’s electronics. In both contexts, these systems require stringent performances such as spectral purity, low phase noise, frequency and temperature stability. In state of the art oscillators the preservation of some of these aspects is jeopardized by specific critical issues, e.g., the sensitivity to load capacitance or the component aging over time. This leaves room for the search of new technologies for their realization. On the other hand, in the last decade electronics has been influenced by a growing number of neuro-inspired mechanisms, which allowed for alternative techniques aimed at solving some classical critical issues.In this paper we present an exploratory study for the development of electronic oscillators based on the neuro-inspired mechanism dynamical relaying, which relies on a structure composed of three delay coupled units (as neurons or even neuron populations) able to resonate and self-organise to generate and maintain a given rhythm with great reliability over a considerable parameter range, showing robustness to noise. We used the recent leaky integrated and fire with latency (LIFL) as neuron model. We have initially developed the mathematical model of the neuro-inspired oscillator, and implemented it using Matlab®; then, we have realized the schematic of such system in PSpice®. Finally, the model has been validated to verify whether it observes the fundamental properties of the dynamical relaying mechanisms described in computational neuroscience studies, and if the circuit implementation presents the same behaviour of the mathematical model.Validation results suggest that the dynamical relaying mechanism can be proficuously taken in consideration as alternative strategy for the design of electronic oscillators

towards neuro inspired electronic oscillators based on the dynamical relaying mechanism

Electronic oscillators are used for the generation of both continuous and discrete signals, playing a fundamental role in today's electronics. In both contexts, these systems require stringent performances such as spectral purity, low phase noise, frequency and temperature stability. In state of the art oscillators the preservation of some of these aspects is jeopardized by specific critical issues, e.g., the sensitivity to load capacitance or the component aging over time. This leaves room for the search of new technologies for their realization. On the other hand, in the last decade electronics has been influenced by a growing number of neuro-inspired mechanisms, which allowed for alternative techniques aimed at solving some classical critical issues. In this paper we present an exploratory study for the development of electronic oscillators based on the neuro-inspired mechanism dynamical relaying , which relies on a structure composed of three delay coupled units (as neurons or even neuron populations) able to resonate and self-organise to generate and maintain a given rhythm with great reliability over a considerable parameter range, showing robustness to noise . We used the recent leaky integrated and fire with latency (LIFL) as neuron model. We have initially developed the mathematical model of the neuro-inspired oscillator , and implemented it using Matlab®; then, we have realized the schematic of such system in PSpice®. Finally, the model has been validated to verify whether it observes the fundamental properties of the dynamical relaying mechanisms described in computational neuroscience studies, and if the circuit implementation presents the same behaviour of the mathematical model. Validation results suggest that the dynamical relaying mechanism can be proficuously taken in consideration as alternative strategy for the design of electronic oscillators

FPGA Implementation of Hand-written Number Recognition Based on CNN

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%

Energy Consumption Saving in Embedded Microprocessors Using Hardware Accelerators

This paper deals with the reduction of power consumption in embedded microprocessors. Computing power and energy efficiency are becoming the main challenges for embedded system applications. This is, in particular, the caseof wearable systems. When the power supply is provided by batteries, an important requirement for these systems is the long service life. This work investigates a method for the reduction of microprocessor energy consumption, based on the use of hardware accelerators. Their use allows to reduce the execution time and to decrease the clock frequency, so reducing the power consumption. In order to provide experimental results, authors analyze a case of study in the field of wearable devices for the processing of ECG signals. The experimental results show that the use of hardware accelerator significantly reduces the power consumption

fpga implementation of hand written number recognition based on cnn

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps. For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%

A Feature Extractor IC for Acoustic Emission Non-destructive Testing

In this paper, we present the design and the implementation of a digital Application Specific Integrated Circuit (ASIC) for Acoustic Emission (AE) non-destructive testing. The AE non-destructive testing method is a diagnostic method used to detect faults in mechanically loaded structures and components. If a structure is subjected to mechanical load or stress, the presence of structural discontinuities releases energy in the form of acoustic emissions through the constituting material. The analysis of these acoustic emissions can be used to determine the presence of faults in several structures. The proposed circuit has been designed for IoT (Internet of Things) applications, and it can be used to simplify the existing procedures adopted for structural integrity verifications of pressurized metal tanks that, in some countries, they are based on periodic checks. The proposed ASIC is provided of Digital Signal Processing (DSP) capabilities for the extraction of the main four parameters used in the AE analysis that are the energy of the signal, the duration of the event, the number of the crossing of a certain threshold and finally the maximum value reached by the AE signal. The circuit is provided of an SPI interface capable of sending and receiving data to/from wireless transceivers to share information on the web. The DSP circuit has been coded in VHDL and synthesized in 90 nm technology using Synopsys. The circuit has been characterized in terms of area, speed, and power consumption. Experimental results show that the proposed circuit presents very low power consumption properties and low area requirements

Design and Evaluation of a Scalable Engine for 3D-FFT Computation in an FPGA Cluster

The Three Dimensional Fast Fourier Transform (3D-FFT) is commonly used to solve the partial differential equations describing the system evolution in several physical phenomena, such as the motion of viscous fluids described by the Navier–Stokes equations. Simulation of such problems requires the use of a parallel High-Performance Computing architecture since the size of the problem grows with the cube of the FFT size, and the representation of the single point comprises several double precision floating- point complex numbers. Modern High-Performance Computing (HPC) systems are considering the inclusion of FPGAs as components of this computing architecture because they can combine effective hardware acceleration capabilities and dedicated communication facilities. Furthermore, the network topology can be optimized for the specific calculation that the cluster must perform, especially in the case of algorithms limited by the data exchange delay between the processors. In this paper, we explore an HPC design that uses FPGA accelerators to compute the 3DFFT. We devise a scalable FFT engine based on a custom radix-2 double-precision core that is used to implement the Decimation in Frequency version of the Cooley–Tukey FFT algorithm. The FFT engine can be adapted to different technology constraints and networking topologies by adjusting the number of cores and configuration parameters in order to minimize the overall calculation time. We compare the various possible configurations with the technological limits of available hardware. Finally, we evaluate the bandwidth required for continuous FFT execution in the APEnet toroidal mesh network