An efficient design or fractional-delay digital FIR filters using the Farrow structure

Fractional-delay digital filter (FD-DF), implemented using the Farrow (1988) structure, is very attractive in providing online tuning delay of digital signals. This paper proposes a new method for the design of such Farrow-based FD-DF using sum-of-powers-of-two (SOPOT) coefficients. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Design examples show that the proposed method can greatly reduce the design time and complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio

FIR variable digital filter with signed power-of-two coefficients

Variable digital filters (VDFs) are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied online. In this paper, we investigate the design of VDFs with discrete coefficients as a means of achieving low complexity and efficient hardware implementation. The filter coefficients are expressed as the sum of signed power-of-two terms with a restriction on the total number of power-of-two for the filter coefficients. An efficient design procedure is proposed that includes an improved method for handling the quantization of the VDF coefficients for both the min-max and the least-square criteria leading to an optimum quantized solution. For the least-square criterion, a reduced search region around the optimum quantized solution is further constructed and the branch and bound method in conjunction with an efficient branch cutting scheme is presented to search for an optimum solution in this reduced region

The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio

Efficient algorithms for arbitrary sample rate conversion with application to wave field synthesis

Arbitrary sample rate conversion (ASRC) is used in many fields of digital signal processing to alter the sampling rate of discrete-time signals by arbitrary, potentially time-varying ratios. This thesis investigates efficient algorithms for ASRC and proposes several improvements. First, closed-form descriptions for the modified Farrow structure and Lagrange interpolators are derived that are directly applicable to algorithm design and analysis. Second, efficient implementation structures for ASRC algorithms are investigated. Third, this thesis considers coefficient design methods that are optimal for a selectable error norm and optional design constraints. Finally, the performance of different algorithms is compared for several performance metrics. This enables the selection of ASRC algorithms that meet the requirements of an application with minimal complexity. Wave field synthesis (WFS), a high-quality spatial sound reproduction technique, is the main application considered in this work. For WFS, sophisticated ASRC algorithms improve the quality of moving sound sources. However, the improvements proposed in this thesis are not limited to WFS, but applicable to general-purpose ASRC problems.Verfahren zur unbeschränkten Abtastratenwandlung (arbitrary sample rate conversion,ASRC) ermöglichen die Änderung der Abtastrate zeitdiskreter Signale um beliebige, zeitvarianteVerhältnisse. ASRC wird in vielen Anwendungen digitaler Signalverarbeitung eingesetzt.In dieser Arbeit wird die Verwendung von ASRC-Verfahren in der Wellenfeldsynthese(WFS), einem Verfahren zur hochqualitativen, räumlich korrekten Audio-Wiedergabe, untersucht.Durch ASRC-Algorithmen kann die Wiedergabequalität bewegter Schallquellenin WFS deutlich verbessert werden. Durch die hohe Zahl der in einem WFS-Wiedergabesystembenötigten simultanen ASRC-Operationen ist eine direkte Anwendung hochwertigerAlgorithmen jedoch meist nicht möglich.Zur Lösung dieses Problems werden verschiedene Beiträge vorgestellt. Die Komplexitätder WFS-Signalverarbeitung wird durch eine geeignete Partitionierung der ASRC-Algorithmensignifikant reduziert, welche eine effiziente Wiederverwendung von Zwischenergebnissenermöglicht. Dies erlaubt den Einsatz hochqualitativer Algorithmen zur Abtastratenwandlungmit einer Komplexität, die mit der Anwendung einfacher konventioneller ASRCAlgorithmenvergleichbar ist. Dieses Partitionierungsschema stellt jedoch auch zusätzlicheAnforderungen an ASRC-Algorithmen und erfordert Abwägungen zwischen Performance-Maßen wie der algorithmischen Komplexität, Speicherbedarf oder -bandbreite.Zur Verbesserung von Algorithmen und Implementierungsstrukturen für ASRC werdenverschiedene Maßnahmen vorgeschlagen. Zum Einen werden geschlossene, analytischeBeschreibungen für den kontinuierlichen Frequenzgang verschiedener Klassen von ASRCStruktureneingeführt. Insbesondere für Lagrange-Interpolatoren, die modifizierte Farrow-Struktur sowie Kombinationen aus Überabtastung und zeitkontinuierlichen Resampling-Funktionen werden kompakte Darstellungen hergeleitet, die sowohl Aufschluss über dasVerhalten dieser Filter geben als auch eine direkte Verwendung in Design-Methoden ermöglichen.Einen zweiten Schwerpunkt bildet das Koeffizientendesign für diese Strukturen, insbesonderezum optimalen Entwurf bezüglich einer gewählten Fehlernorm und optionaler Entwurfsbedingungenund -restriktionen. Im Gegensatz zu bisherigen Ansätzen werden solcheoptimalen Entwurfsmethoden auch für mehrstufige ASRC-Strukturen, welche ganzzahligeÜberabtastung mit zeitkontinuierlichen Resampling-Funktionen verbinden, vorgestellt.Für diese Klasse von Strukturen wird eine Reihe angepasster Resampling-Funktionen vorgeschlagen,welche in Verbindung mit den entwickelten optimalen Entwurfsmethoden signifikanteQualitätssteigerungen ermöglichen.Die Vielzahl von ASRC-Strukturen sowie deren Design-Parameter bildet eine Hauptschwierigkeitbei der Auswahl eines für eine gegebene Anwendung geeigneten Verfahrens.Evaluation und Performance-Vergleiche bilden daher einen dritten Schwerpunkt. Dazu wirdzum Einen der Einfluss verschiedener Entwurfsparameter auf die erzielbare Qualität vonASRC-Algorithmen untersucht. Zum Anderen wird der benötigte Aufwand bezüglich verschiedenerPerformance-Metriken in Abhängigkeit von Design-Qualität dargestellt.Auf diese Weise sind die Ergebnisse dieser Arbeit nicht auf WFS beschränkt, sondernsind in einer Vielzahl von Anwendungen unbeschränkter Abtastratenwandlung nutzbar

Digital Filters and Signal Processing

Digital filters, together with signal processing, are being employed in the new technologies and information systems, and are implemented in different areas and applications. Digital filters and signal processing are used with no costs and they can be adapted to different cases with great flexibility and reliability. This book presents advanced developments in digital filters and signal process methods covering different cases studies. They present the main essence of the subject, with the principal approaches to the most recent mathematical models that are being employed worldwide

Variable Fractional Digital Delay Filter on Reconfigurable Hardware

This thesis describes a design for a variable fractional delay (VFD) finite impulse reponse (FIR) filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters have been implemented using a fixed structure in software based upon the order of the filter. This fixed structure restricts the range of valid fractional delay values permitted by the filter. This proposed design implements an order-scalable FIR filter, permitting fractionally delayed signals of widely varying integer sizes. Furthermore, the proposed design of this thesis builds upon the traditional Lagrange interpolator FIR filter using either asoftware-based coefficient computational unit or hardware-based coefficient computational unit in reconfigurable hardware for updating the FIR coefficients in real-time. Traditional Lagrange interpolator FIR filters have only permitted fixed fractional delay. However, by leveraging todays (2012) low-cost high performance reconfigurable hardware, an FIR-based fractional delay filter was created to permit varying fractional delay. A software/hardware hybrid VFD filter was prototyped using the Xilinx System Generator toolkit. The resulting real-time VFD FIR filter was tested usingSystem Generator, as well as Xilinx ISE and ModelSim.M.S., Computer Engineering -- Drexel University, 201

Low-complexity filter for software-defined radio by modulated interpolated coefficient decimated filter in a hybrid farrow

Realising a low-complexity Farrow channelisation algorithm for multi-standard receivers in software-defined radio is a challenging task. A Farrow filter operates best at low frequencies while its performance degrades towards the Nyquist region. This makes wideband channelisation in software-defined radio a challenging task with high computational complexity. In this paper, a hybrid Farrow algorithm that combines a modulated Farrow filter with a frequency response interpolated coefficient decimated masking filter is proposed for the design of a novel filter with low computational complexity. A design example shows that the HFarrow filter bank achieved multiplier reduction of 50%, 70% and 64%, respectively, in comparison with non-uniform modulated discrete Fourier transform (NU MDFT FB), coefficient decimated filter bank (CD FB) and interpolated coefficient decimated (ICDM) filter algorithms. The HFarrow filter bank is able to provide the same number of sub-band channels as other algorithms such as non-uniform modulated discrete Fourier transform (NU MDFT FB), coefficient decimated filter bank (CD FB) and interpolated coefficient decimated (ICDM) filter algorithms, but with less computational complexity.https://www.mdpi.com/journal/sensorsam2023Electrical, Electronic and Computer Engineerin

Digital resampling and timing recovery in QAM systems

Digital resampling is a process that converts a digital signal from one sampling rate to another. This process is performed by means of interpolating between the input samples to produce output samples at an output sampling rate. The digital interpolation process is accomplished with an interpolation filter. The problem of resampling digital signals at an output sampling rate that is incommensurate with the input sampling rate is the first topic of this thesis. This problem is often encountered in practice, for example in multiplexing video signals from different sources for the purpose of distribution. There are basically two approaches to resample the signals. Both approaches are thoroughly described and practical circuits for hardware implementation are provided. A comparison of the two circuits shows that one circuit requires a division to compute the new sampling times. This time scaling operation adds complexity to the implementation with no performance advantage over the other circuit, and makes the 'division free' circuit the preferred one for resampling. The second topic of this thesis is performance analysis of interpolation filters for Quadrature Amplitude Modulation (QAM) signals in the context of timing recovery. The performance criterion of interest is Modulation Error Ratio (MER), which is considered to be a very useful indicator of the quality of modulated signals in QAM systems. The methodology of digital resampling in hardware is employed to describe timing recovery circuits and propose an approach to evaluate the performance of interpolation filters. A MER performance analysis circuit is then devised. The circuit is simulated with MATLAB/Simulink as well as implemented in Field Programmable Gate Array (FPGA). Excellent agreement between results obtained from simulation and hardware implementation proves the validity of the methodology and practical application of the research works

Wordlength determination algorithms for hardware implementation of linear time invariant systems with prescribed output accuracy

This paper proposes two novel algorithms for optimizing the hardware resources in finite wordlength implementation of linear time invariant systems. The hardware complexity is measured by the exact internal wordlength used for each intermediate data. The first algorithm formulates the design problem as a constrained optimization, from which an analytic closed-form solution of the internal wordlengths subject to a prescribed output accuracy can be determined by the Lagrange multiplier method. The second algorithm is based on a discrete optimization method called the Marginal Analysis method, and it yields the desired wordlengths in integer values. Both approaches are found to be very effective and they are well-suited to large scale systems such as software radio receivers. Design examples show that the proposed algorithms offer better results and a lower design complexity than conventional methods. © 2005 IEEE.published_or_final_versio