Command vector memory systems: high performance at low cost

The focus of this paper is on designing both a low cost and high performance, high bandwidth vector memory system that takes advantage of modern commodity SDRAM memory chips. To successfully extract the full bandwidth from SDRAM parts, we propose a new memory system organization based on sending commands to the memory system as opposed to sending individual addresses. A command specifies, in a few bytes, a request for multiple independent memory words. A command is similar to a burst found in DRAM memories, but does not require the memory words to be consecutive. The command is sent to all sections of the memory array simultaneously, thus not requiring a crossbar in the proper sense. Our simulations show that this command based memory system can improve performance over a traditional SDRAM-based memory system by factors that range between 1.15 up to 1.54. Moreover, in many cases, the command memory system outperforms even the best SRAM memory system under consideration. Overall the command based memory system achieves similar or better results than a 10 ns SRAM memory system (a) using fewer banks and (b) using memory devices that are between 15 to 60 times cheaper.Peer ReviewedPostprint (published version

Design and Implementation of an RNS-based 2D DWT Processor

No abstract availabl

High Performance Power Spectrum Analysis Using a FPGA Based Reconfigurable Computing Platform

Power-spectrum analysis is an important tool providing critical information about a signal. The range of applications includes communication-systems to DNA-sequencing. If there is interference present on a transmitted signal, it could be due to a natural cause or superimposed forcefully. In the latter case, its early detection and analysis becomes important. In such situations having a small observation window, a quick look at power-spectrum can reveal a great deal of information, including frequency and source of interference. In this paper, we present our design of a FPGA based reconfigurable platform for high performance power-spectrum analysis. This allows for the real-time data-acquisition and processing of samples of the incoming signal in a small time frame. The processing consists of computation of power, its average and peak, over a set of input values. This platform sustains simultaneous data streams on each of the four input channels.Comment: 5 pages, 3 figures. Published in the Proceedings of the IEEE International conference on Reconfigurable Computing and FPGAs (ReConFig 2006). Article also available at http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4100006&isnumber=409995

An FPGA-based real-time event sampler

This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modified to match the behavior of different kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family

Classification and analysis of predictable memory patterns

The verification complexity of real-time requirements in embedded systems grows exponentially with the number of applications, as resource sharing prevents independent verification using simulation-based approaches. Formal verification is a promising alternative, although its applicability is limited to systems with predictable hardware and software. SDRAM memories are common examples of essential hardware components with unpredictable timing behavior, typically preventing use of formal approaches. A predictable SDRAM controller has been proposed that provides guarantees on bandwidth and latency by dynamically scheduling memory patterns, which are statically computed sequences of SDRAM commands. However, the proposed patterns become increasingly inefficient as memories become faster, making them unsuitable for DDR3 SDRAM. This paper extends the memory pattern concept in two ways. Firstly, we introduce a burst count parameter that enables patterns to have multiple SDRAM bursts per bank, which is required for DDR3 memories to be used efficiently. Secondly, we present a classification of memory pattern sets into four categories based on the combination of patterns that cause worst-case bandwidth and latency to be provided. Bounds on bandwidth and latency are derived that apply to all pattern types and burst counts, as opposed to the single case covered by earlier work. Experimental results show that these extensions are required to support the most efficient pattern sets for many use-cases. We also demonstrate that the burst count parameter increases efficiency in presence of large requests and enables a wider range of real-time requirements to be satisfied

An SDRAM test education package that embeds the factory equipment into the e-learning server

SDRAM (Synchronous Dynamic Random Access Memory) demand has grown exponentially since the 1980s, as a result of technological factors and new areas of application, particularly concerning communication and consumer electronics. The SDRAM market represented in 2007 c. 20% of the total semiconductor business and is seen as a strategic area, justifying private and public investment in the western and far-eastern economic communities. SDRAM test education is therefore an important subject, but very high purchase and maintenance costs keep test equipment beyond reach of most university test courses. This paper presents a pilot project addressing an SDRAM test education course developed jointly by Qimonda and the University of Porto (FEUP), where the company offers remote access to one if its Advantest SDRAM automatic test equipments. Access to this remote tester was embedded into the Moodle e-learning server that supports a new course entitled Electronic Systems Testing (TSEL), which is part of the Integrated Masters degree on Electrical and Computer Engineering at FEUP. The excellent feedback received from students encouraged us to extend this cooperation into an educational network, which is also introduced in this paper