Resolution analysis of switching converter models for hardware-in-the-loop

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. O. Goñi, A. Sánchez, E. Todorovich, Á. de Castro, "Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop", IEEE Transactions on Industrial Informatics, vol. 10, no.2, pp.1162 - 1170, May, 2014This work proposes two methods to determine the resolution of state variables in models of switching-mode power converters. The target models are intended for hardware-in-the-loop, i.e., closed-loop emulation using a model of the power converter implemented in digital hardware with the controller in its final implementation. The focus here is on the resolution of fixed-point models, although the results can also be applied to the significand resolution in floating-point representation. The first method is based on the simulation, provides the designer with the optimum resolution values, and guarantees that using the resolution, the converter will behave as it was specified. The second method is fast but conservative, intended for applications without hard constraints of area and speed. Despite the simplicity of the second method, its results, although slightly overestimated, have been demonstrated to be correct by the results of the first method. A boost converter for the power factor correction is used as an application example. As the converter model is intended for field-programmable gate array implementation, its area and maximum clock frequency are also analyzed. In this application example, the results show that the area grows linearly with the number of bits of each state variable, and the clock frequency is dominated by the width of one of the variables.This work was partially supported by the Agencia Nacional de Promoción Científica y Tecnológica, Argentina, through Project PICT 2009 - 0041

A comparison of simulation and hardware-in-the-loop alternatives for digital control of power converters

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. A. Sánchez, Á. de Castro, J. Garrido, "A Comparison of Simulation and Hardware-in-the- Loop Alternatives for Digital Control of Power Converters", IEEE Transactions on Industrial Informatics, vol. 8, no. 3, pp. 491 - 500, Aug. 2012Debugging digital controllers for power converters can be a problem because there are both digital and analog components. This paper focuses on debugging digital controllers to be implemented in Field Programmable Gate Arrays or Application Specific Integrated Circuits, which are designed in hardware description languages. Four methods are proposed and described. All of them allow simulation, and two methods also allow emulation-synthesizing the model of the converter to run the complete closed-loop system in actual hardware. The first method consists in using a mixed analog and digital simulator. This is the easiest alternative for the designer, but simulation time can be a problem, specially for long simulations like those necessary in power factor correction or when the controller is very complex, for example, with embedded processors. The alternative is to use pure digital models, generating a digital model of the power converter. Three methods are proposed: real type, float type and fixed point models (in the latter case including hand-coded and automatic-coded descriptions). Float and fixed point models are synthesizable, so emulation is possible, achieving speedups over 20 000. The results obtained with each method are presented, highlighting the advantages and disadvantages of each one. Apart from that, an analysis of the necessary resolution in the variables is presented, being the main conclusion that 32-bit floating point is not enough for medium and high switching frequencies

Sub-harmonic oscillations attenuation in hardware-in-the-loop models using the Integration Oversampling Method

Hardware-in-the-loop (HIL) technology has become widespread for testing purposes, gaining special importance in micro-grids and renewable energy. One of the main challenges in HIL technology is its use in mid or high-frequency applications. In those cases, oversampling gate signals is a must to obtain enough accuracy and avoid undesirable sub-harmonic oscillations in the emulation that would not appear in a real scenario or offline electrical simulation. However, handling the extra information obtained through oversampling increases significantly the complexity of switched models since the oversampling methods deal with more than one sample per simulation step. It leads to extra design effort if the models are designed ad-hoc or increased hardware resources when using vendor tools that implement oversampling techniques. In both cases, oversampling traditionally implies an increase in the overall cost of the HIL system. This paper proposes the Integration Oversampling Method (IOM), which manages the extra information obtained through oversampling with a minimum impact on the models’ complexity. In fact, the power model is not changed at all and uses just one switch state per simulation step. The method consists in adding a small hardware block in the input of the gate signals. Using the additional information obtained through oversampling, it generates a set of switch states in every simulation step that minimizes the integrated error in the input reading. The experimental results obtained through an NI myRIO device show clearly enhanced performance when using IOM both in transient and steady-state operation. At the same time, the additional hardware resources necessary for IOM implementation are negligibl

Comparison of different design alternatives for hardware-in-the-loop of power converters

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effor

Development of a MATLAB/Simulink - Arduino environment for experimental practices in control engineering teaching

This project presents the steps followed when implementing a platform based on MATLAB/Simulink and Arduino for the restoration of digital control practices. During this project, an Arduino shield has being designed. Along with this, a web page has also been created where all the material done during all this project is available and can be freely used. So anyone interested on doing a project can have a starting point instead of starting a project from scratch, which most of times this results hard to implement. Taking all this into account, the document is structured in the following manner. The first chapter talks about the hardware used and designed. The second one explains the software used and the configurations done on the laboratory’s PCs. After that, the web page Duino-Based Learning is explained, where you can find the five projects carried out in the "Control Automàtic" subject with their corresponding results. In this section too, as an additional research, the implemented indirect adaptive control will be explained, where the parameter estimation has been done by the Recursive Least Square algorithm. The last four sections before presenting the conclusions of the work, correspond to a satisfaction questionnaire done to the teachers that have used the setup, the costs and saves of the project, the environmental impact and the planning of the project respectively

Analysis of the aliasing effect caused in hardware-in-the-loop when reading PWM inputs of power converters

Hardware-in-the-loop (HIL) systems are commonly used to debug controllers in closed-loop operation. Therefore, the frequency response of the emulated subsystem is of special relevance. Undesirable oscillations can appear as a consequence of digitally sampling the switch control signals in power converter HIL models. These oscillations at relatively low frequencies, below the switching frequency, may confound the closed-loop operation and, therefore, the appropriate debugging of the controller. This paper shows that the lost information when an HIL model reads a PWM signal may create some output offset error or steady-state fluctuations, especially when the switching period and the sampling step get closer. The aliasing frequencies produced by the input sampling are calculated, and the small-signal analysis explains the relation between the output oscillation and the input PWM sub-harmonics. The output error spectrum proves that the main error sub-harmonics have the same aliasing frequency components. Both captured oscilloscope results obtained by an NI myRIO device and MATLAB simulations verify that significant distortions can be seen in the output inductor current if there is a low aliasing frequency in the digital version of the input PWM signal read by the HIL mode

Emulator of a boost converter for educational purposes

Project-based learning (PBL) is proposed for the development of a Hardware-in-the-Loop (HIL) platform and the design of its digital controller for an undergraduate course on Digital Electronic Systems. The objective for students is the design of a digitally controlled HIL Boost converter, a digital pulse-width modulator (DPWM) and a current mode controller, implemented in field-programmable gate array (FPGA) devices. To this end, the di erent parts of the project are developed and evaluated, maximizing the use of FPGA resources in the design of the HIL and DPWM blocks, and applying design techniques that minimize the use of the digital resources used in the design of the controller. Students are equipped with a new individualized educational experience, allowing them to test their technical competence and knowledge in an environment close to the reality of the industry

Analysis of resolution in feedback signals for hardware-in-the-loop models of power converters

One of the main techniques for debugging power converters is hardware-in-the-loop (HIL), which is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common design platforms due to their acceleration capability. In this case, the widths of the signals have to be carefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the best options because although the design time is high, it allows the personalization of the number of bits in every signal. The representation of state variables in power converters has been previously studied, however other signals, such as feedback signals, can also have a big influence because they transmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of the number of bits in the feedback signals of a boost converter, but the conclusions can be extended to other power converters. The purpose of this work is to study how many bits are necessary in order to avoid the loss of information, but also without wasting bits. Errors of the state variables are obtained with di erent sizes of feedback signals. These show that the errors in each state variable have similar patterns. When the number of bits increases, the error decreases down to a certain number of bits, where an almost constant error appears. However, when the bits decrease, the error increases linearly. Furthermore, the results show that there is a direct relation between the number of bits in feedback signals and the inputs of the converter in the global error. Finally, a design criterion is given to choose the optimum width for each feedback signal, without wasting bit

Full- & Reduced-Order State-Space Modeling of Wind Turbine Systems with Permanent-Magnet Synchronous Generator

Wind energy is an integral part of nowadays energy supply and one of the fastest growing sources of electricity in the world today. Accurate models for wind energy conversion systems (WECSs) are of key interest for the analysis and control design of present and future energy systems. Existing control-oriented WECSs models are subject to unstructured simplifications, which have not been discussed in literature so far. Thus, this technical note presents are thorough derivation of a physical state-space model for permanent magnet synchronous generator WECSs. The physical model considers all dynamic effects that significantly influence the system's power output, including the switching of the power electronics. Alternatively, the model is formulated in the $(a,b,c)$- and $(d,q)$-reference frame. Secondly, a complete control and operation management system for the wind regimes II and III and the transition between the regimes is presented. The control takes practical effects such as input saturation and integral windup into account. Thirdly, by a structured model reduction procedure, two state-space models of WECS with reduced complexity are derived: a non-switching model and a non-switching reduced-order model. The validity of the models is illustrated and compared through a numerical simulation study.Comment: 23 pages, 11 figure