Modeling the Impact of Process Variation on Resistive Bridge Defects

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (V) and effective mobility (ueff) where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE

Variation aware analysis of bridging fault testing

This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate drive strength parameters are analyzed regarding their process variation induced influence on test quality. The impact of process variation on test quality is studied in terms of test escapes and measured by a robustness metric. It is shown that some bridges are sensitive to process variation in terms of logic behavior, but such variation does not necessarily compromise test quality if the test has high robustness. Experimental results of Monte-Carlo simulation based on recent process variation statistics are presented for ISCAS85 and -89 benchmark circuits, using a 45nm gate library and realistic bridges. The results show that tests generated without consideration of process variation are inadequate in terms of test quality, particularly for small test sets. On the other hand, larger test sets detect more of the logic faults introduced by process variation and have higher test quality

Compact Structural Test Generation for Analog Macros

A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IV-converter macro design. Parameters of so-called test configurations are optimized for detection of faults in a fault-list and an optimal selection algorithm results in determining the best test set. The distribution of the results along the parameter-axes of the test configurations is investigated to identify a collapsed high-quality test se

Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation

As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide.Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens.The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy

Tradeoffs between AC power quality and DC bus ripple for 3-phase 3-wire inverter-connected devices within microgrids

Visions of future power systems contain high penetrations of inverters which are used to convert power from dc (direct current) to ac (alternating current) or vice versa. The behavior of these devices is dependent upon the choice and implementation of the control algorithms. In particular, there is a tradeoff between dc bus ripple and ac power quality. This study examines the tradeoffs. Four control modes are examined. Mathematical derivations are used to predict the key implications of each control mode. Then, an inverter is studied both in simulation and in hardware at the 10 kVA scale, in different microgrid environments of grid impedance and power quality. It is found that voltage-drive mode provides the best ac power quality, but at the expense of high dc bus ripple. Sinusoidal current generation and dual-sequence controllers provide relatively low dc bus ripple and relatively small effects on power quality. High-bandwidth dc bus ripple minimization mode works well in environments of low grid impedance, but is highly unsuitable within higher impedance microgrid environments and/or at low switching frequencies. The findings also suggest that the certification procedures given by G5/4, P29 and IEEE 1547 are potentially not adequate to cover all applications and scenarios

Enhancement of Transient Stability of DFIG Based Variable Speed Wind Generator Using Diode-bridge-type Non-superconducting Fault Current Limiter and Resistive Solid State Fault Current Limiter

The application of doubly-fed induction generator (DFIG) is very effective in the fast-growing wind generator (WG) market. The foremost concern for the DFIG based WG system is to maintain the transient stability during fault, as the stator of the DFIG is directly connected to the grid. Therefore, transient stability enhancement of the DFIG is very important. In this work, a diode-bridge-type nonsuperconducting fault current limiter (NSFCL) and resistive solid-state fault current limiter (R-type SSFCL) are examined to augment the transient stability of the DFIG based WG system.In simulations, temporary balanced and unbalanced faults were applied in the test system to investigate the proposed NSFCL and the R-type SSFCL transient stability performance. Besides a DC resistive superconducting fault current limiter (SFCL), bridge-type fault current limiter (BFCL) and series dynamic braking resistor (SDBR) are also considered to compare their performance with the proposed NSFCL and R-type SSFCL. These simulations were performed with Matlab/Simulink software. Simulation results clearly indicate that the NSFCL and R-type SSFCL enhances the transient stability of the DFIG based WG. Moreover, the NSFCL works better than the DC resistive SFCL, BFCL and SDBR in every aspect and R-type SSFCL works better than the SDBR in all aspect

Investigation into voltage and process variation-aware manufacturing test

Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

Manufacturing defects that do not affect the functional operation of low power Integrated Circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R ≳ 10MΩ(weak bridges) and bridges of R ≲ 10MΩ (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively

Analysis, testing, and evaluation of faulted and unfaulted Wye, Delta, and open Delta connected electromechanical actuators

Mathematical models capable of simulating the transient, steady state, and faulted performance characteristics of various brushless dc machine-PSA (power switching assembly) configurations were developed. These systems are intended for possible future use as primemovers in EMAs (electromechanical actuators) for flight control applications. These machine-PSA configurations include wye, delta, and open-delta connected systems. The research performed under this contract was initially broken down into the following six tasks: development of mathematical models for various machine-PSA configurations; experimental validation of the model for failure modes; experimental validation of the mathematical model for shorted turn-failure modes; tradeoff study; and documentation of results and methodology

Protection of modern distribution systems

“Motivated by the potential for improvements in the electric distribution system’s protection schemes, this work examined the challenges facing protection schemes due to the integration of Distributed Generators (DGs). Traditional protection schemes for radial distribution systems were designed based on the unidirectional power flow from the source down to the loads. Protective devices typically use are overcurrent relays, autoreclosers, fuses, and circuit breakers. However, these protective schemes may no longer be sufficient to ensure correct operation in the new era of distribution systems integrated by DGs. This research investigated the impact of DGs that might mislead the protection schemes in distribution systems. Understanding these impacts are helpful for improving protection schemes solution methodologies. This work also presented multiple solutions for protection schemes aimed at mitigating the negative impacts of integrating DGs into radial distribution systems. The first proposed solution provided improvements for distance relays (DRs) that were proposed recently to protect radial distribution feeders (RDFs). This solution consisted of three new methods to accurately calculate the measured positive-sequence impedance by DR in the presence of the infeed effect. These methods depended only on local measurements making them cost-effective and easy to implement compared to other solutions that depend on communication links. The second solution proposed a new approach to control inverter-based DGs (IB- DGs). This approach limited the fault current in distribution systems by controlling single-phase inverters that connect distributed generators to distribution systems. Finally, this research proposed an accurate and reliable model for the resistive superconducting fault current limiter (SFCL). The performances of the proposed methods were demonstrated with radial distribution system models in PSCAD™/EMTDC™”--Abstract, page iv