Weighted p-bits for FPGA implementation of probabilistic circuits

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware

A Survey on Security Threats and Countermeasures in IEEE Test Standards

International audienceEditor's note: Test infrastructure has been shown to be a portal for hackers. This article reviews the threats and countermeasures for IEEE test infrastructure standards

Anti-Tamper Method for Field Programmable Gate Arrays Through Dynamic Reconfiguration and Decoy Circuits

As Field Programmable Gate Arrays (FPGAs) become more widely used, security concerns have been raised regarding FPGA use for cryptographic, sensitive, or proprietary data. Storing or implementing proprietary code and designs on FPGAs could result in the compromise of sensitive information if the FPGA device was physically relinquished or remotely accessible to adversaries seeking to obtain the information. Although multiple defensive measures have been implemented (and overcome), the possibility exists to create a secure design through the implementation of polymorphic Dynamically Reconfigurable FPGA (DRFPGA) circuits. Using polymorphic DRFPGAs removes the static attributes from their design; thus, substantially increasing the difficulty of successful adversarial reverse-engineering attacks. A variety of dynamically reconfigurable methodologies exist for implementation that challenge designers in the reconfigurable technology field. A Hardware Description Language (HDL) DRFPGA model is presented for use in security applications. The Very High Speed Integrated Circuit HDL (VHSIC) language was chosen to take advantage of its capabilities, which are well suited to the current research. Additionally, algorithms that explicitly support granular autonomous reconfiguration have been developed and implemented on the DRFPGA as a means of protecting its designs. Documented testing validates the reconfiguration results and compares power usage, timing, and area estimates from a conventional and DRFPGA model

Configurable pseudo noise radar imaging system enabling synchronous MIMO channel extension

In this article, we propose an evolved system design approach to ultra-wideband (UWB) radar based on pseudo-random noise (PRN) sequences, the key features of which are its user-adaptability to meet the demands provided by desired microwave imaging applications and its multichannel scalability. In light of providing a fully synchronized multichannel radar imaging system for short-range imaging as mine detection, non-destructive testing (NDT) or medical imaging, the advanced system architecture is presented with a special focus put on the implemented synchronization mechanism and clocking scheme. The core of the targeted adaptivity is provided by means of hardware, such as variable clock generators and dividers as well as programmable PRN generators. In addition to adaptive hardware, the customization of signal processing is feasible within an extensive open-source framework using the Red Pitaya ® data acquisition platform. A system benchmark in terms of signal-to-noise ratio (SNR), jitter, and synchronization stability is conducted to determine the achievable performance of the prototype system put into practice. Furthermore, an outlook on the planned future development and performance improvement is provided

On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Design of Stochastic Computing Architectures using Integrated Optics

Approximate computing (AC) is an emerging computing approach that allows to trade off design energy efficiency with computing accuracy. It targets error resilient applications, such as image processing, where energy consumption is of major concern. Stochastic computing (SC) is an approximate computing paradigm that leads to energy efficient and reduced hardware complexity designs. In this approach, data is represented as probabilities in bit streams format. The main drawback of this computing paradigm is the intrinsic serial processing of bit streams, which negatively impacts the processing time. Nanophotonics technology is characterized by high bandwidth and high signals propagation speed, which has the potential to support the electrical domain in computations to speed up the processing rate. The major issues in optical computing (OC) remain the large size of silicon photonics devices, which impact the design scalability. In this thesis, we propose, for the first time, an optical stochastic computing (OSC) approach, where we aim to design SC architectures using integrated optics. For this purpose, we propose a methodology that has libraries for optical processing and interfaces, e.g., bit stream generator. We design all-optical gates for the computation and develop transmission models for the architectures. The methodology allows for design space exploration of technological and system-level parameters to optimize design performance, i.e., energy efficiency, computing accuracy, and latency, for the targeted application. This exploration leads to multiple design options that satisfy different design requirements for the selected application. The optical processing libraries include designing a polynomial architecture that can execute any arbitrary single input function. We explore the design parameters by implementing a Gamma correction application for image processing. Results show a 4.5x increase in the errors, which leads to 47x energy saving and 16x faster processing speed. We propose a reconfigurable polynomial architecture to adapt design order at run-time. The design allows the execution of high order polynomial functions for better accuracy or multiple low order functions to increase throughput and energy efficiency. Finally, we propose the design of combinational filters. The purpose is to investigate the design of cascaded gates architectures using photonic crystal (PhC) nanocavities. We use this device to design a Sobel edge detection filter for image processing. The resulting architecture shows 0.85nJ/pixel energy consumption and 51.2ns/pixel processing time. The optical interface libraries include designing different architectures of stochastic number generators (SNG) that are either electrical-optical or all-optical to generate the bit streams. We compare these SNGs in terms of computing accuracy and energy efficiency. The results show that all implementations can lead to the same level of computing accuracy. Moreover, using an all-optical SNG to design a fully optical 8-bit adder results in 98% reduction in hardware complexity and 70% energy saving compared to a conventional optical design

Built-In Self-Test Quality Assessment Using Hardware Fault Emulation in FPGAs

This paper addresses the problem of test quality assessment, namely of BIST solutions, implemented in FPGA and/or in ASIC, through Hardware Fault Emulation (HFE). A novel HFE methodology and tool is proposed, that, using partial reconfiguration, efficiently measures the quality of the BIST solution. The proposed HFE methodology uses Look-Up Tables (LUTs) fault models and is performed using local partial reconfiguration for fault injection on Xilinx(TM) Virtex and/or Spartan FPGA components, with small binary files. For ASIC cores, HFE is used to validate test vector selection to achieve high fault coverage on the physical structure. The methodology is fully automated. Results on ISCAS benchmarks and on an ARM core show that HFE can be orders of magnitude faster than software fault simulation or fully reconfigurable hardware fault emulation

Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation