Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters

This paper presents a research line oriented to develop methodologies that takes advantage of hardware description languages in order to simplify the design of power converters that employ digital control techniques. The methodology focuses on setting the adequate communications among subsystems in order to simplify the change of the levels of abstraction of the subsystem’s models (from the conceptual level to the actual electric + synthesizable code). Changing the level of abstraction in the design process pretends: first to provide useful models at early designing steps; second, to optimize the simulation of the system, and at same time optimize the verification step

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

In this thesis, the author proposes a circular system development model which considers all the stages in a typical development process for industrial systems. In particular, the present work shows that the use of virtual prototyping at early stages of the system development may reduce the overall design and verification effort by allowing the exploration of the complete system architecture, and uncovering integration issues early on. The modeling techniques of this research are based on VHDL-AMS, yet supporting other modeling languages such as C/C++, SPICE, and Verilog-AMS, together with integrated simulation tools. Contrasting with conventional approaches, it is shown that the proposed methodology is adapted for small-scale Cyber-Physical Systems (CPS) design and verification thanks to the modularity and scalability of the modeling approach. The proposed modeling techniques enable seamlessly the CPS design together with the implementation of their subsystems. In particular, the contribution of this work improves the virtual prototyping approach that has been successfully used during the development of smart electrical sensors and monitoring equipment for high and medium voltage applications. The design of the measurement and self-calibration circuits of a medium voltage current sensor based on the Rogowski coil transducer is presented as an example. The proposed small-scale CPS design methodology based on virtual prototyping, namely VP-based design methodology, uses important theoretical concepts from layered design, component-based design, and platform-based design. These foundations are the basis to build a modeling methodology that provides a vehicle that can be used to improve system verification towards correct-by-design systems. The main contributions of this research are: the re-definition of the system development lifecycle by using a virtual prototyping methodology; the design and implementation of a model library that maximizes the reuse of computational models and their related IP; and a set of VHDL-AMS modeling guidelines established with the purpose of improving the modularity and scalability of virtual prototypes. These elements are key for supporting the introduction of virtual prototyping into industrial companies that can thoroughly profit from this approach, but cannot commit a specific team to the creation, support, and maintenance of computational models and its dedicated infrastructure. Thanks to the progressive nature of the proposed methodology, virtual prototypes can indeed be introduced with relatively low initial effort and enhanced over time. The presented methodology and its infrastructure may grow into a bidirectional communication medium between non-expert system designers (i.e. system architects and virtual integrators) and domain specialists such as mechanical designers, power electrical designers, embedded-electronics designers, and software designers. The proposed design methodology advocates the reduction of the CPS design complexity by the implementation of a meet-in-the-middle approach for system-level modeling. In this direction, the modeling techniques introduced in this work facilitate the architectural design space exploration, critical cross-domain variable analysis (especially important in the component interfaces), and system-level optimization and verification

The Second NASA Formal Methods Workshop 1992

The primary goal of the workshop was to bring together formal methods researchers and aerospace industry engineers to investigate new opportunities for applying formal methods to aerospace problems. The first part of the workshop was tutorial in nature. The second part of the workshop explored the potential of formal methods to address current aerospace design and verification problems. The third part of the workshop involved on-line demonstrations of state-of-the-art formal verification tools. Also, a detailed survey was filled in by the attendees; the results of the survey are compiled

Simulation multi-moteurs multi-niveaux pour la validation des spécifications système et optimisation de la consommation

This work aims at system-level modelling a defined transceiver for Bluetooth Low energy (BLE) system using SystemC-AMS. The goal is to analyze the relationship between the transceiver performance and the accurate energy consumption. This requires the transceiver model contains system-level simulation speed and the low-level design block power consumption and other RF specifications. The Meet-in-the-Middle approach and the Baseband Equivalent method are chosen to achieve the two requirements above. A global simulation of a complete BLE system is achieved by integrating the transceiver model into a SystemC-TLM described BLE system model which contains the higher-than-PHY levels. The simulation is based on a two BLE devices communication system and is run with different BLE use cases. The transceiver Bit-Error-Rate and the energy estimation are obtained at the end of the simulation. First, we modelled and validated each block of a BT transceiver. In front of the prohibitive simulation time, the RF blocks are rewritten by using the BBE methodology, and then refined in order to take into account the non-linearities, which are going to impact the couple consumption, BER. Each circuit (each model) is separately verified, and then a first BLE system simulation (point-to-point between a transmitter and a receiver) has been executed. Finally, the BER is finally estimated. This platform fulfills our expectations, the simulation time is suitable and the results have been validated with the circuit measurement offered by Riviera Waves Company. Finally, two versions of the same transceiver architecture are modelled, simulated and comparedCe travail vise la modélisation au niveau système, en langage SystemC-AMS, et la simulation d'un émetteur-récepteur au standard Bluetooth Low Energy (BLE). L'objectif est d'analyser la relation entre les performances, en termes de BER et la consommation d'énergie du transceiver. Le temps de simulation d’un tel système, à partir de cas d’étude (use case) réaliste, est un facteur clé pour le développement d’une telle plateforme. De plus, afin d’obtenir des résultats de simulation le plus précis possible, les modèles « haut niveau » doivent être raffinés à partir de modèles plus bas niveau où de mesure. L'approche dite Meet-in-the-Middle, associée à la méthode de modélisation équivalente en Bande Base (BBE, BaseBand Equivalent), a été choisie pour atteindre les deux conditions requises, à savoir temps de simulation « faible » et précision des résultats. Une simulation globale d'un système de BLE est obtenue en intégrant le modèle de l'émetteur-récepteur dans une plateforme existante développée en SystemC-TLM. La simulation est basée sur un système de communication de deux dispositifs BLE, en utilisant différents scénarios (différents cas d'utilisation de BLE). Dans un premier temps nous avons modélisé et validé chaque bloc d’un transceiver BT. Devant le temps de simulation prohibitif, les blocs RF sont réécrits en utilisant la méthodologie BB, puis raffinés afin de prendre en compte les non-linéarités qui vont impacter le couple consommation, BER. Chaque circuit (chaque modèle) est vérifié séparément, puis une première simulation système (point à point entre un émetteur et un récepteur) est effectué

Efficient verification/testing of system-on-chip through fault grading and analog behavioral modeling

textThis dissertation presents several cost-effective production test solutions using fault grading and mixed-signal design verification cases enabled by analog behavioral modeling. Although the latest System-on-Chip (SOC) is getting denser, faster, and more complex, the manufacturing technology is dominated by subtle defects that are introduced by small-scale technology. Thus, SOC requires more mature testing strategies. By performing various types of testing, better quality SoC can be manufactured, but test resources are too limited to accommodate all those tests. To create the most efficient production test flow, any redundant or ineffective tests need to be removed or minimized. Chapter 3 proposes new method of test data volume reduction by combining the nonlinear property of feedback shift register (FSR) and dictionary coding. Instead of using the nonlinear FSR for actual hardware implementation, the expanded test set by nonlinear expansion is used as the one-column test sets and provides big reduction ratio for the test data volume. The experimental results show the combined method reduced the total test data volume and increased the fault coverage. Due to the increased number of test patterns, total test time is increased. Chapter 4 addresses a whole process of functional fault grading. Fault grading has always been a ”desire-to-have” flow because it can bring up significant value for cost saving and yield analysis. However, it is very hard to perform the fault grading on the complex large scale SOC. A commercial tool called Z01X is used as a fault grading platform, and whole fault grading process is coordinated and each detailed execution is performed. Simulation- based functional fault grading identifies the quality of the given functional tests against the static faults and transition delay faults. With the structural tests and functional tests, functional fault grading can indicate the way to achieve the same test coverage by spending minimal test time. Compared to the consumed time and resource for fault grading, the contribution to the test time saving might not be acceptable as very promising, but the fault grading data can be reused for yield analysis and test flow optimization. For the final production testing, confident decisions on the functional test selection can be made based on the fault grading results. Chapter 5 addresses the challenges of Package-on-Package (POP) testing. Because POP devices have pins on both the top and the bottom of the package, the increased test pins require more test channels to detect packaging defects. Boundary scan chain testing is used to detect those continuity defects by relying on leakage current from the power supply. This proposed test scheme does not require direct test channels on the top pins. Based on the counting algorithm, minimal numbers of test cycles are generated, and the test achieved full test coverage for any combinations of pin-to-pin shortage defects on the top pins of the POP package. The experimental results show about 10 times increased leakage current from the shorted defect. Also, it can be expanded to multi-site testing with less test channels for high-volume production. Fault grading is applied within different structural test categories in Chapter 6. Stuck-at faults can be considered as TDFs having infinite delay. Hence, the TDF Automatic Test Pattern Generation (ATPG) tests can detect both TDFs and stuck-at faults. By removing the stuck-at faults being detected by the given TDF ATPG tests, the tests that target stuck-at faults can be reduced, and the reduced stuck-at fault set results in fewer stuck-at ATPG patterns. The structural test time is reduced while keeping the same test coverage. This TDF grading is performed with the same ATPG tool used to generate the stuck-at and TDF ATPG tests. To expedite the mixed-signal design verification of complex SoC, analog behavioral modeling methods and strategies are addressed in Chapter 7 and case studies for detailed verification with actual mixed-signal design are ad- dressed in Chapter 8. Analog modeling effort can enhance verification quality for a mixed-signal design with less turnaround time, and it enables compatible integration of the mixed-signal design cores into the SoC. The modeling process may reveal any potential design errors or incorrect testbench setup, and it results in minimizing unnecessary debugging time for quality devices. Two mixed-signal design cases were verified by me using the analog models. A fully hierarchical digital-to-analog converter (DAC) model is implemented and silicon mismatches caused by process variation are modeled and inserted into the DAC model, and the calibration algorithm for the DAC is successfully verified by model-based simulation at the full DAC-level. When the mismatch amount is increased and exceeded the calibration capability of the DAC, the simulation results show the increased calibration error with some outliers. This verification method can identify the saturation range of the DAC and predict the yield of the devices from process variation. A phase-locked loop (PLL) design cases were also verified by me using the analog model. Both open-loop PLL model and closed-loop PLL model cases are presented. Quick bring-up of open-loop PLL model provides low simulation overhead for widely-used PLLs in the SOC and enables early starting of design verification for the upper-level design using the PLL generated clocks. Accurate closed-loop PLL model is implemented for DCO-based PLL design, and the mixed-simulation with analog models and schematic designs enables flexible analog verification. Only focused analog design block is set to the schematic design and the rest of the analog design is replaced by the analog model. Then, this scaled-down SPICE simulation is performed about 10 times to 100 times faster than full-scale SPICE simulation. The analog model of the focused block is compared with the scaled-down SPICE simulation result and the quality of the model is iteratively enhanced. Hence, the analog model enables both compatible integration and flexible analog design verification. This dissertation contributes to reduce test time and to enhance test quality, and helps to set up efficient production testing flows. Depending on the size and performance of CUT, proper testing schemes can maximize the efficiency of production testing. The topics covered in this dissertation can be used in optimizing the test flow and selecting the final production tests to achieve maximum test capability. In addition, the strategies and benefits of analog behavioral modeling techniques that I implemented are presented, and actual verification cases shows the effectiveness of analog modeling for better quality SoC products.Electrical and Computer Engineerin

Mixed-signal integrated circuits design and validation for automotive electronics applications

Automotive electronics is a fast growing market. In a field primarily dominated by mechanical or hydraulic systems, over the past few decades there has been exponential growth in the number of electronic components incorporated into automobiles. Partly thanks to the advance in high voltage smart power processes in nowadays cars is possible to integrate both power/high voltage electronics and analog/digital signal processing circuitry thus allowing to replace a lot of mechanical systems with electro-mechanical or fully electronic ones. High level modeling of complex electronic systems is gaining importance relatively to design space exploration, enabling shorter design and verification cycles, allowing reduced time-to-market. A high level model of a resistor string DAC to evaluate nonlinearities has been developed in MATLAB environment. As a test case for the model, a 10 bit resistive DAC in 0.18um is designed and the results were compared with the traditional transistor level approach. Then we face the analysis and design of a fundamental block: the bandgap voltage reference. Automotive requirements are tough, so the design of the voltage reference includes a pre-regulation part of the battery voltage that allows to enhance overall performances. Moreover an analog integrated driver for an automotive application whose architecture exploits today’s trends of analog-digital integration allowing a greater range of flexibility allowing high configurability and fast prototipization is presented. We covered also the mixed-signal verification approach. In fact, as complexity increases and mixed-signal systems become more and more pervasive, test and verification often tend to be the bottleneck in terms of time effort. A complete flow for mixed-signal verification using VHDL-AMS modeling and Python scripting is presented as an alternative to complex transistor level simulations. Finally conclusions are drawn

Design of a dependable interlock system for linear colliders

For high energy accelerators, the interlock system is a key part of the machine protection. The interlock principle is to inhibit the beam either on failure of critical equipment and/or on low beam quality evaluation. The dependability of such a system is the most critical parameter. This thesis presents the design of an dependable interlock system for linear collider with an application to the CLIC (Compact Linear Collider) project. This design process is based on the IEEE 1220 standard and is is divided in four steps. First,the specifications are established, with a focus on the dependability, more precisely the reliability and the availability of the system. The second step is the design proposal based on a functional analysis, the CLIC and interfaced systems architecture. Third, the feasibility study is performed, applying the concepts in an accelerator facility. Finally, the last step is the hardware verification. Its aim is to prove that the proposed design is able to reach the requirements

Methoden und Beschreibungssprachen zur Modellierung und Verifikation vonSchaltungen und Systemen: MBMV 2015 - Tagungsband, Chemnitz, 03. - 04. März 2015

Der Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) findet nun schon zum 18. mal statt. Ausrichter sind in diesem Jahr die Professur Schaltkreis- und Systementwurf der Technischen Universität Chemnitz und das Steinbeis-Forschungszentrum Systementwurf und Test. Der Workshop hat es sich zum Ziel gesetzt, neueste Trends, Ergebnisse und aktuelle Probleme auf dem Gebiet der Methoden zur Modellierung und Verifikation sowie der Beschreibungssprachen digitaler, analoger und Mixed-Signal-Schaltungen zu diskutieren. Er soll somit ein Forum zum Ideenaustausch sein. Weiterhin bietet der Workshop eine Plattform für den Austausch zwischen Forschung und Industrie sowie zur Pflege bestehender und zur Knüpfung neuer Kontakte. Jungen Wissenschaftlern erlaubt er, ihre Ideen und Ansätze einem breiten Publikum aus Wissenschaft und Wirtschaft zu präsentieren und im Rahmen der Veranstaltung auch fundiert zu diskutieren. Sein langjähriges Bestehen hat ihn zu einer festen Größe in vielen Veranstaltungskalendern gemacht. Traditionell sind auch die Treffen der ITGFachgruppen an den Workshop angegliedert. In diesem Jahr nutzen zwei im Rahmen der InnoProfile-Transfer-Initiative durch das Bundesministerium für Bildung und Forschung geförderte Projekte den Workshop, um in zwei eigenen Tracks ihre Forschungsergebnisse einem breiten Publikum zu präsentieren. Vertreter der Projekte Generische Plattform für Systemzuverlässigkeit und Verifikation (GPZV) und GINKO - Generische Infrastruktur zur nahtlosen energetischen Kopplung von Elektrofahrzeugen stellen Teile ihrer gegenwärtigen Arbeiten vor. Dies bereichert denWorkshop durch zusätzliche Themenschwerpunkte und bietet eine wertvolle Ergänzung zu den Beiträgen der Autoren. [... aus dem Vorwort

RIFEL - Ripple and Electromagnetic Fields in Electric Vehicles

The electrical system in an electrified vehicle consists of high voltage (HV) components interacting in a complex way. The switching interaction in the power electronics results in ripple causing electromagnetic fields, disturbing other electronics and degradation of components. An overview of this can first be obtained when a physical system is built which could lead to unintentional over- or under dimensioning of HV components. This lack of information within the electrical system can lead to late verifications in the project causing substantial cost if changes are needed. This project aims at improving early evaluation of new concepts, create tools and build the necessary competence for a virtual system model that includes the key HV components: battery, electrical motor and power electronics, a simple load along with cable and connectors. This virtual model shall be able to simulate voltage and current ripple generated by the power electronics, initially in a frequency range up to 100 kHz. Results from the simulations shall be presented both in time and frequency domain as well as be expressed in RMS values for easier comparison to measured results. Some of the more important findings are briefly summarised below;For the high voltage battery, the electrical characteristics up to a frequency of roughly 1000 Hz was well determined using an impedance spectroscopy instrument at cell level and then multiplied by the numbers of cells.\ua0 However for finding the impedance behaviour for frequencies above 1000 Hz, the determination must be done on the battery pack level since bus bars and other component in the complete battery pack will be dominating in this frequency range. From measurements of differential mode impedance in high voltage cables it is found that it is important that the mutual inductance between the centre conductor and shield is included in the model to describe cable impedance below 10 kHz properly.The control of the inverter is very important for the overall behaviour and in this project SVM was used which has been shown to give the lowest current and voltage ripple of the traditional switching schemes. And for the machine model, the temperature variations must be taken into account since the machine parameters has been found to vary with ~20 % over the specified temperature range.The system model is found to agree well with rig measurements well up to 1 MHz with regards to both currents and voltages at the DC and AC sides. Furthermore, measurements in a real car match those in the rig. For time domain simulations, it was decided to use Ansys Simplorer since it can handle the inverter and the electrical machine simulations very well and for frequency domain simulations, it was decided to use LTspice since it is freeware, has support for AC-sweeps, improved switching compared to other SPICE-simulators, and is easy to use.Magnetic field simulations have been calculated and compared to measurements in the driveline rig at Chalmers. It was a good match across the investigated frequency range 10 Hz to 100 kHz.In this project, only internally developed component models were considered. To expand the functionality of the system modelling tool, international interface standards such as the Functional Mockup Interface (FMI) need to be investigated. Consequently, it would be a good idea to include additional automotive OEMs as well as suppliers and software vendors in future research collaborations