Final report on the evaluation of RRM/CRRM algorithms

Deliverable public del projecte EVERESTThis deliverable provides a definition and a complete evaluation of the RRM/CRRM algorithms selected in D11 and D15, and evolved and refined on an iterative process. The evaluation will be carried out by means of simulations using the simulators provided at D07, and D14.Preprin

Capacity and coverage trade-off in WCDMA environments with repeaters deployment

radio planning, WCDMA, repeaters, capacity and coverageThis work derives the analytic expression of the feasibility condition for the uplink of a WCDMA mobile communications system with repeaters deployment in a multiservice environment with a general heterogeneous layout. In particular, a compact closed expression for the admission region is presented, suitable for a system where the users belong to an arbitrary number of different service classes. A tradeoff between capacity and coverage arises and it has been analysed both theoretically and by means of simulations. Different parameters are shown to have a major impact and their adjustment is discussed.Peer ReviewedPostprint (published version

Capacity and coverage tradeoff in WCDMA environments with repeaters deployment.

Postprint (published version

Enhanced analysis of WCDMA networks with repeaters deployment

This paper addresses the analysis of WCDMA systems with repeaters deployment. A generic and compact expression for up- and downlinks evaluation has been mathematically derived so that transmission powers and other radio resource management parameters can be calculated without simplifications. In particular, the real different path delays, taking into account the repeaters presence and the finite nature of the time window of Rake receivers are considered. This allows an enhanced analysis with respect to classical approaches from a system level viewpoint. Furthermore, higher reliable and accurate predictions on network performance can be obtained, which can be remarkably useful for network planning and management. By using these expressions, relevant network parameters have been evaluated and compared with the ones obtained using the classical approximations. The differences in the obtained metrics are highlighted, putting in evidence the improvement provided by the proposed analysis.Peer Reviewe

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast