Design and implementation of decoders for error correction in high-speed communication systems

This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures. A new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. In order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. Finally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.Esta tesis se ha centrado en el diseño e implementación de decodificadores binarios basados en códigos de comprobación de paridad de baja densidad (LDPC) válidos para los sistemas de comunicación modernos de alta velocidad. Los conceptos básicos de códigos LDPC, sus prestaciones y cuellos de botella, en términos de complejidad y eficiencia hardware, fueron analizados para los principales algoritmos de decisión soft y decisión hard (como Min-Sum, Optimized 2-bit Min-Sum y Reliability-based iterative Majority-Logic). La complejidad y prestaciones de estos algoritmos se han mejorado para conseguir arquitecturas hardware eficientes. Se ha propuesto un nuevo algoritmo de decodificación llamado One-Minimum Min-Sum. Éste reduce considerablemente la complejidad de las ecuaciones de actualización del nodo de comprobación del algoritmo Min-Sum. El segundo mínimo se ha estimado a partir del valor del primer mínimo por medio de una aproximación lineal, la cuál permite un ajuste dinámico. El algoritmo Optimized 2-bit Min-Sum se ha modificado para ser inicializado con los valores LLR e introducir la información extrínseca en los mensajes enviados desde los nodos variables. La ecuación del nodo variable de este algoritmo ha sido reformulada para reducir su complejidad. Ambos algoritmos fueron probados para el código (2048,1723) RS-based LDPC y para el código (16129,15372) LDPC utilizando un emulador hardware implementado en un dispositivo FPGA. Éstos han alcanzado unas prestaciones de BER muy cercanas a las del algoritmo Min-Sum evitando, además, la aparición temprana del fenómeno denominado suelo del error. Con el objetivo de mostrar las ventajas hardware de los algoritmos propuestos, los decodificadores se implementaron en hardware utilizando tecnología CMOS de 90 nm y en dispositivos FPGA basados en dos tipos de arquitecturas: completamente paralela y parcialmente paralela utilizando el método de actualización por capas horizontales. Los resultados muestran que los decodificadores propuestos e implementados son más eficientes en área-tiempo que otros decodificadores publicados y que la baja complejidad del algoritmo Modified Optimized 2-bit Min-Sum permite la implementación de decodificadores en los dispositivos FPGA actuales consiguiendo una tasa de 10 Gbps. Finalmente, se ha presentado un nuevo algoritmo de decodificación de decisión hard, el Historical-Extrinsic Reliability-Based Iterative Decoder. Este algoritmo introduce la nueva idea de considerar los votos de decisión hard como decisión soft para calcular la información extrínseca de iteracions anteriores. Este algoritmo es adecuado para códigos de alta velocidad y mejora el rendimiento BER de los algoritmos RBI-MLGD anteriores, con una complejidad similar.Aquesta tesi s'ha centrat en el disseny i implementació de descodificadors binaris basats en codis de comprovació de paritat de baixa densitat (LDPC) vàlids per als sistemes de comunicació moderns d'alta velocitat. Els conceptes bàsics de codis LDPC, les seues prestacions i colls de botella, en termes de complexitat i eficiència hardware, van ser analitzats pels principals algoritmes de decisió soft i decisió hard (com el Min-Sum, Optimized 2-bit Min-Sum y Reliability-based iterative Majority-Logic). La complexitat i prestacions d'aquests algoritmes s'han millorat per aconseguir arquitectures hardware eficients. S'ha proposat un nou algoritme de descodificació anomenat One-Minimum Min-Sum. Aquest redueix considerablement la complexitat de les equacions d'actualització del node de comprovació del algoritme Min-Sum. El segon mínim s'ha estimat a partir del valor del primer mínim per mitjà d'una aproximació lineal, la qual permet un ajust dinàmic. L'algoritme Optimized 2-bit Min-Sum s'ha modificat per ser inicialitzat amb els valors LLR i introduir la informació extrínseca en els missatges enviats des dels nodes variables. L'equació del node variable d'aquest algoritme ha sigut reformulada per reduir la seva complexitat. Tots dos algoritmes van ser provats per al codi (2048,1723) RS-based LDPC i per al codi (16129,15372) LDPC utilitzant un emulador hardware implementat en un dispositiu FPGA. Aquests han aconseguit unes prestacions BER molt properes a les del algoritme Min-Sum evitant, a més, l'aparició primerenca del fenomen denominat sòl de l'error. Per tal de mostrar els avantatges hardware dels algoritmes proposats, els descodificadors es varen implementar en hardware utilitzan una tecnologia CMOS d'uns 90 nm i en dispositius FPGA basats en dos tipus d'arquitectures: completament paral·lela i parcialment paral·lela utilitzant el mètode d'actualització per capes horitzontals. Els resultats mostren que els descodificadors proposats i implementats són més eficients en àrea-temps que altres descodificadors publicats i que la baixa complexitat del algoritme Modified Optimized 2-bit Min-Sum permet la implementació de decodificadors en els dispositius FPGA actuals obtenint una taxa de 10 Gbps. Finalment, s'ha presentat un nou algoritme de descodificació de decisió hard, el Historical-Extrinsic Reliability-Based Iterative Decoder. Aquest algoritme presenta la nova idea de considerar els vots de decisió hard com decisió soft per calcular la informació extrínseca d'iteracions anteriors. Aquest algoritme és adequat per als codis d'alta taxa i millora el rendiment BER dels algoritmes RBI-MLGD anteriors, amb una complexitat similar.Català Pérez, JM. (2017). Design and implementation of decoders for error correction in high-speed communication systems [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/86152TESI

Decoder based on Parallel Genetic Algorithm and Multi-objective Optimization for Low Density Parity Check Codes

Genetic algorithms are powerful search techniques that are used successfully to solve problems in many different disciplines. This article introduces a new Parallel Genetic Algorithm for decoding LDPC codes (PGAD). The results show that the proposed algorithm gives large gains over the Sum-Product decoder, which proves its efficiency. We also show that the fitness function must be improved by Multi-objective Optimization, for this, we applied the Weighted Sum method to improve PGAD, this new version is called (MOGAD) gives higher performance compared to one. Keywords: Parallel Genetic Algorithms decoder, Sum-Product decoder, Fitness Function, LDPC codes, Error correcting codes, Multi-objective optimization, Weighted sum method

A modified belief-propagation decoder for the parallel decoding of product codes

In this dissertation a modification to the belief-propagation algorithm is presented. The algorithm modifies the belief-propagation algorithm to allow for the parallel decoding of product codes. The algorithm leverages the fact that each component code in the product code can be independently decoded because the codewords are encoded by independent and identically distributed (i.i.d.) processes. The algorithm maximises the parellelisation by decoding all the component codes in each dimension in parallel. In order to facilitate this process we developed new additional stages which are added to the belief-propagation algorithm: the codeword reliability estimation, the belief-aggregation and the exit test stages. The parallel product code decoder o ers a 0.2 dB worsening of the decoding BER performance when compared to the best serial decoder. However, the parallel belief-propagation decoder o ers a 7.26 time speedup on an eight-core processor, which is 0.91 of the theoretical maximum of eight for an eight-core processor

Channel Coding in Molecular Communication

This dissertation establishes and analyzes a complete molecular transmission system from a communication engineering perspective. Its focus is on diffusion-based molecular communication in an unbounded three-dimensional fluid medium. As a basis for the investigation of transmission algorithms, an equivalent discrete-time channel model (EDTCM) is developed and the characterization of the channel is described by an analytical derivation, a random walk based simulation, a trained artificial neural network (ANN), and a proof of concept testbed setup. The investigated transmission algorithms cover modulation schemes at the transmitter side, as well as channel equalizers and detectors at the receiver side. In addition to the evaluation of state-of-the-art techniques and the introduction of orthogonal frequency-division multiplexing (OFDM), the novel variable concentration shift keying (VCSK) modulation adapted to the diffusion-based transmission channel, the lowcomplex adaptive threshold detector (ATD) working without explicit channel knowledge, the low-complex soft-output piecewise linear detector (PLD), and the optimal a posteriori probability (APP) detector are of particular importance and treated. To improve the error-prone information transmission, block codes, convolutional codes, line codes, spreading codes and spatial codes are investigated. The analysis is carried out under various approaches of normalization and gains or losses compared to the uncoded transmission are highlighted. In addition to state-of-the-art forward error correction (FEC) codes, novel line codes adapted to the error statistics of the diffusion-based channel are proposed. Moreover, the turbo principle is introduced into the field of molecular communication, where extrinsic information is exchanged iteratively between detector and decoder. By means of an extrinsic information transfer (EXIT) chart analysis, the potential of the iterative processing is shown and the communication channel capacity is computed, which represents the theoretical performance limit for the system under investigation. In addition, the construction of an irregular convolutional code (IRCC) using the EXIT chart is presented and its performance capability is demonstrated. For the evaluation of all considered transmission algorithms the bit error rate (BER) performance is chosen. The BER is determined by means of Monte Carlo simulations and for some algorithms by theoretical derivation

D11.2 Consolidated results on the performance limits of wireless communications

Deliverable D11.2 del projecte europeu NEWCOM#The report presents the Intermediate Results of N# JRAs on Performance Limits of Wireless Communications and highlights the fundamental issues that have been investigated by the WP1.1. The report illustrates the Joint Research Activities (JRAs) already identified during the first year of the project which are currently ongoing. For each activity there is a description, an illustration of the adherence and relevance with the identified fundamental open issues, a short presentation of the preliminary results, and a roadmap for the joint research work in the next year. Appendices for each JRA give technical details on the scientific activity in each JRA.Peer ReviewedPreprin

Single-Frequency Network Terrestrial Broadcasting with 5GNR Numerology

L'abstract è presente nell'allegato / the abstract is in the attachmen

Hardware-Conscious Wireless Communication System Design

The work at hand is a selection of topics in efficient wireless communication system design, with topics logically divided into two groups.One group can be described as hardware designs conscious of their possibilities and limitations. In other words, it is about hardware that chooses its configuration and properties depending on the performance that needs to be delivered and the influence of external factors, with the goal of keeping the energy consumption as low as possible. Design parameters that trade off power with complexity are identified for analog, mixed signal and digital circuits, and implications of these tradeoffs are analyzed in detail. An analog front end and an LDPC channel decoder that adapt their parameters to the environment (e.g. fluctuating power level due to fading) are proposed, and it is analyzed how much power/energy these environment-adaptive structures save compared to non-adaptive designs made for the worst-case scenario. Additionally, the impact of ADC bit resolution on the energy efficiency of a massive MIMO system is examined in detail, with the goal of finding bit resolutions that maximize the energy efficiency under various system setups.In another group of themes, one can recognize systems where the system architect was conscious of fundamental limitations stemming from hardware.Put in another way, in these designs there is no attempt of tweaking or tuning the hardware. On the contrary, system design is performed so as to work around an existing and unchangeable hardware limitation. As a workaround for the problematic centralized topology, a massive MIMO base station based on the daisy chain topology is proposed and a method for signal processing tailored to the daisy chain setup is designed. In another example, a large group of cooperating relays is split into several smaller groups, each cooperatively performing relaying independently of the others. As cooperation consumes resources (such as bandwidth), splitting the system into smaller, independent cooperative parts helps save resources and is again an example of a workaround for an inherent limitation.From the analyses performed in this thesis, promising observations about hardware consciousness can be made. Adapting the structure of a hardware block to the environment can bring massive savings in energy, and simple workarounds prove to perform almost as good as the inherently limited designs, but with the limitation being successfully bypassed. As a general observation, it can be concluded that hardware consciousness pays off

Channel coding for highly efficient transmission in wireless local area network

Seit ihrer Wiederentdeckung haben die Low Density Parity Check (LDPC) Codes ein hohes Interesse erfahren, da sie mit niedrigem Aufwand für die Dekodierung fast die Kanalkapazität erreichen. Daher sind sie ein vielversprechendes Kanalcodierungsschema für zukünftige drahtlose Anwendungen. Sie weisen allerdings noch den Nachteil eines hohen Enkodierungsaufwandes auf. Die Einwicklung eines mit geringem Aufwand implementierbaren LDPC Codes mit guten Leistungen stellt noch eine große Herausforderung dar. Die Nutzbarkeit der potenziellen Eigenschaften von LDPC-Codes im Bezug auf die technischen Randbedingungen gerade bei drahtlosen lokalen Netzwerken (Wireess Local Area Network - WLAN) wirft dabei besonders interessante Fragestellungen auf. Die vorliegende Dissertation konzentriert sich auf drei große Themen bezüglich der Erforschung von LDPC Codes, nämlich die Charakterisierung des Codes mittels Umfangsmaßverteilung (Girth Degree Distribution), den niedrigen Enkodierungsaufwand mittels strukturierter Codekonstruktion sowie die verbesserte Decodierungskonvergenz mittels eines Zwei-Phasen Dekodierungsverfahrens. Im ersten Teil der Dissertation wird ein neues Konzept zur Beurteilung von Codes eingeführt. Es basiert auf der Umfangsmaßverteilung. Dieses Konzept kombiniert die Ideen des klassischen Konzeptes - basierend auf dem Umfang (Girth) - mit denen des Knotenmaßes (Node Degree) und wird zur Charakterisierung und zur Abschätzung der Leistungsfähigkeit des Codes eingesetzt. Zur Erkennung und Berechnung des Umfangs wird ein einfacher, baumbasierter Suchalgorithmus eingeführt. Dieses Konzept ermöglicht eine effizientere Leistungsabschätzung als das der alleinigen Verwendung des Umfangs. Es wird gezeigt, dass das Umfangsmaß bei der Ermittlung der Leistung des Codes eine wesentlich größere Rolle spielt als der Umfang. Im Rahmen dieser Untersuchungen fällt als weiteres Ergebnis an, dass die Existenz von kurzen Schleifen der Länge 4 die Leistungsfähigkeit des Codes nicht beeinträchtigt. Der zweite Teil der Dissertation beschäftigt sich mit einem einfachen Verfahren für die Konstruktion einer Gruppe von LDPC Codes, die bei einem relativ niedrigen Enkodierungsaufwand dennoch eine gute Leistung aufweist. Die Kombination einer Treppestruktur in Verbindung mit Permutationsmatrizen führt zu einer sehr einfachen Implementierung, ohne dass ein erheblicher Leistungsverlust auftritt. Der resultierende Enkodierer kann ausschließlich mit einer sehr einfachen Schaltung aus Schieberegistern implementiert werden. Die Leistungsfähigkeit des entstehenden Codes ist mit der des unregelmäßigen MacKay-Codes vergleichbar. In kurzer Kodelänge übertreffen sie sogar einige bekannte strukturierte Codes. Allerdings sind die vorgeschlagenen Codes suboptimal im Vergleich mit den optionalen LDPC Codes für WLAN, sofern niedrige Coderaten betrachtet werden. Sie erweisen sich aber als ebenbürtig bei höheren Coderaten. Diese Leistungsfähigkeit wird von den hier vorgeschlagenen Codes mit relativ niedrigem Enkodierungsaufwand erreicht. Letztendlich wird im dritten Teil der Dissertation ist ein Verfahren zur Steigerung der Decodierungskonvergenz beim Einsatz von LDPC Codes in Kombination mit Modulationsverfahren hoher Wertigkeit vorgestellt. Das Zwei-Phasen Dekodierverfahren wird zur Verbesserung der Bit-Zuverlässigkeit im Dekodierungsprozess eingeführt. Dieses bewirkt eine Reduktion der benötigten Dekodierungsschritte ohne Leistungsverlust. Erreicht wird dies durch die Verwendung der Ergebnisse einer ersten Dekodierungsphase als erneute Eingabe für eine zweite Dekodierungsphase. Die optimale Kombination der durchzuführenden Iterationen beider Dekodierungsphasen kann die Anzahl der insgesamt benötigten Iteration im Durchschnitt reduzieren. Dieses Verfahren zeigt seine Wirksamkeit im Wasserfallbereich des Signal-Rausch-Verhältnisses. -Since their rediscovery, Low Density Parity Check (LDPC) codes sparked high interests due to their capacity-approaching performance achieved through their low decoding complexity. Therefore, they are considered as promising scheme for channel coding in future wireless application. However, they still constitute disadvantage in their high encoding complexity. The research on practical LDPC codes with good performance is quite challenging. In this direction their potential characteristics are explored with respect to the technical requirement of wireless local area network (WLAN). This thesis is focused on three topics, which correspond to three major issues in the research of LDPC codes: code characterization with girth degree distribution, low encoding complexity with structured construction, and higher decoding convergence with two-stage decoding scheme. In the first part of the thesis, a novel concept of girth degree is introduced. This concept combines the idea of the classical concept of girth with node degree. The proposed concept is used to characterize the codes and measure their performance. A simple treebased search algorithm is applied to detect and count the girth degree. The proposed concept is more effective than the classical concept of girth in measuring the performance. It shows that the girth degree plays more significant role than the girth it self, in determining the code performance. Furthermore, the existence of short-four-cycles to some extent is not harmful to degrade the code performances. The second part deals with a simple method for constructing a class of LDPC codes, which pose relative low encoding complexity but show good performance. The combination of the stair structure and the permutation matrices, which are constructed based on the proposed method, yields very simple implementation in encoding process within encoder. The resulting encoder can be implemented using relatively simple shiftregister circuits. Their performance is comparable with that of irregular MacKay codes. In short code length, they outperform some well-established structured codes. The performance of the proposed codes is comparable with the optional LDPC codes for WLAN at higher code rates. However, the proposed codes are relatively suboptimal at lower code rate. Such performance is achieved by the proposed codes in lower encoding complexity In the third part, a method for enhancing the decoding convergence for high coded modulation system is introduced. The two-stage decoding scheme is proposed to improve bit reliabilities in decoding process leading to reduced decoding iteration without performance losses. This is achieved by making use of the output from the first decoding stage as the additional input for the second decoding stage. The optimal combination of the maximal iteration of both decoding stages is capable of reducing the average iteration. This method shows its efficiency at the waterfall region of signal-to-noise-ratio

Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs

Increasing static random access memory (SRAM) bitcell density is a major driving force for semiconductor technology scaling. The industry standard 2x reduction in SRAM bitcell area per technology node has lead to a proliferation in memory intensive applications as greater memory system capacity can be realized per unit area. Coupled with this increasing capacity is an increasing SRAM system-level soft error rate (SER). Soft errors, caused by galactic radiation and radioactive chip packaging material corrupt a bitcell’s data-state and are a potential cause of catastrophic system failures. Further, reductions in device geometries, design rules, and sensitive node capacitances increase the probability of multiple adjacent bitcells being upset per particle strike to over 30% of the total SER below the 45 nm process node. Traditionally, these upsets have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling however, errors beyond this setup begin to emerge. Although more powerful ECCs exist, they come at an increased overhead in terms of area and latency. Additionally, interleaving adds complexity to the system and may not always be feasible for the given architecture. In this thesis, a new class of ECC targeted toward adjacent multi-bit upsets (MBU) is proposed and analyzed. These codes present a tradeoff between the currently popular single error correcting-double error detecting (SEC-DED) ECCs used in SRAMs (that are unable to correct MBUs), and the more robust multi-bit ECC schemes used for MBU reliability. The proposed codes are evaluated and compared against other ECCs using a custom test suite and multi-bit error channel model developed in Matlab as well as Verilog hardware description language (HDL) implementations synthesized using Synopsys Design Compiler and a commercial 65 nm bulk CMOS standard cell library. Simulation results show that for the same check-bit overhead as a conventional 64 data-bit SEC-DED code, the proposed scheme provides a corrected-SER approximately equal to the Bose-Chaudhuri- Hocquenghem (BCH) double error correcting (DEC) code, and a 4.38x improvement over the SEC-DED code in the same error channel. While, for 3 additional check-bits (still 3 less than the BCH DEC code), a triple adjacent error correcting version of the proposed code provides a 2.35x improvement in corrected-SER over the BCH DEC code for 90.9% less ECC circuit area and 17.4% less error correction delay. For further verification, a 0.4-1.0 V 75 kb single-cycle SRAM macro protected with a programmable, up-to-3-adjacent-bit-correcting version of the proposed ECC has been fab- ricated in a commercial 28 nm bulk CMOS process. The SRAM macro has undergone neu- tron irradiation testing at the TRIUMF Neutron Irradiation Facility in Vancouver, Canada. Measurements results show a 189x improvement in SER over an unprotected memory with no ECC enabled and a 5x improvement over a traditional single-error-correction (SEC) code at 0.5 V using 1-way interleaving for the same number of check-bits. This is compa- rable with the 4.38x improvement observed in simulation. Measurement results confirm an average active energy of 0.015 fJ/bit at 0.4 V, and average 80 mV reduction in VDDMIN across eight packaged chips by enabling the ECC. Both the SRAM macro and ECC circuit were designed for dynamic voltage and frequency scaling for both nominal and low voltage applications using a full-custom circuit design flow