894 research outputs found

    Botnets and Distributed Denial of Service Attacks

    Get PDF
    With their ever increasing malicious capabilities and potential to infect a vast majority of computers on the Internet, botnets are emerging as the single biggest threat to Internet security. The aim of this project is to perform a detailed analysis of botnets and the vulnerabilities exploited by them to spread themselves and perform various malicious activities such as DDoS attacks. DDoS attacks are without doubt the most potent form of attacks carried out by botnets. In order to better understand this growing phenomenon and develop effective counter measures, it is necessary to be able to simulate DDoS attacks in a controlled environment. Simulating a DDoS attack with control over various simulation and attack parameters will give us insights into how attacks achieve stealth and avoid detection. A detailed analysis of existing DDoS defense strategies and proposals combined with the insights derived from simulation should enable us to come up with innovative and feasible solutions to prevent and mitigate DDoS attacks carried out using Botnet

    Imperial College Computing Student Workshop

    Get PDF

    Final report of the Construction Industry Institute, Hong Kong research project on reinventing the Hong Kong construction industry for its sustainable development

    Get PDF
    Author name used in this publication: Andrew N. BaldwinAuthor name used in this publication: Y. H. ChiangAuthor name used in this publication: Joyce W. S. CheungAuthor name used in this publication: Joanne W. S. NgConstruction Industry Institute-Hong Kong Report, no. 132008-2009 > Academic research: not refereed > Research book or monograph (author)Other Versio

    Topological Games and Hyperspace Topologies

    Get PDF
    The paper proposes a uni?ed description of hypertopologies, i.e. topologies on the nonempty closed subsets of a topological space, based on the notion of approach spaces introduced by R. Lowen. As a special case of this description we obtain the abstract hit-and-miss, proximal hit-and-miss and a big portion of weak hypertopologies generated by gap and excess functionals (including the Wijsman topology and the ?nite Hausdorff topology), respectively. We also give characterizations of separation axioms T0,T1,T2,T3 and complete regularity as well as of metrizability of hypertopologies in this general setting requiring no additional conditions. All this is done to provide a background for proving the main results in Section 4, where we apply topological games (the Banach–Mazur and the strong Choquet game, respectively) to establish various properties of hypertopologies; in particular we characterize Polishness of hypertopologies in this general settin

    Hammering towards QED

    Get PDF
    This paper surveys the emerging methods to automate reasoning over large libraries developed with formal proof assistants. We call these methods hammers. They give the authors of formal proofs a strong “one-stroke” tool for discharging difficult lemmas without the need for careful and detailed manual programming of proof search. The main ingredients underlying this approach are efficient automatic theorem provers that can cope with hundreds of axioms, suitable translations of the proof assistant’s logic to the logic of the automatic provers, heuristic and learning methods that select relevant facts from large libraries, and methods that reconstruct the automatically found proofs inside the proof assistants. We outline the history of these methods, explain the main issues and techniques, and show their strength on several large benchmarks. We also discuss the relation of this technology to the QED Manifesto and consider its implications for QED-like efforts.Blanchette’s Sledgehammer research was supported by the Deutsche Forschungs- gemeinschaft projects Quis Custodiet (grants NI 491/11-1 and NI 491/11-2) and Hardening the Hammer (grant NI 491/14-1). Kaliszyk is supported by the Austrian Science Fund (FWF) grant P26201. Sledgehammer was originally supported by the UK’s Engineering and Physical Sciences Research Council (grant GR/S57198/01). Urban’s work was supported by the Marie-Curie Outgoing International Fellowship project AUTOKNOMATH (grant MOIF-CT-2005-21875) and by the Netherlands Organisation for Scientific Research (NWO) project Knowledge-based Automated Reasoning (grant 612.001.208).This is the final published version. It first appeared at http://jfr.unibo.it/article/view/4593/5730?acceptCookies=1

    De-escalation: A Necessity for the Survival of Law Enforcement

    Get PDF
    The topic of de-escalation has gained a great deal of attention in recent years due to a high number of high-profile tragic events that involved great bodily harm or the use of deadly force. De-escalation tactics are nonphysical skills used to prevent a potentially dangerous situation from escalating into a physical confrontation. There is no shortage of news stories highlighting the conflict between law enforcement officers, law enforcement agencies, and the general public. Many times, conflict can be eliminated or reduced by breaking down barriers that may exist between law enforcement agencies and the communities they serve. Many agencies have community outreach programs designed to involve diverse members of the community to act as a conduit to a better law enforcement/community relationship. Today’s law enforcement officer has to be functioning at a high level at all times while making sound ethical decisions. Society expects officers to enforce laws in an attempt to keep order and discipline, while at the same time being morally sensible with strong values. By having sound code of conduct policies and handling ethics complaints appropriately, agencies will build trust externally as well as within their agencies. Critical incidents in law enforcement that receive widespread attention have a way of impacting how peace officers perform their official duties. In an attempt to influence peace officer’s conduct, behaviors, or actions, federal laws provide guidance and state statutes are often amended or created to facilitate compliance and promote de-escalation. This paper will attempt to examine the topic of de-escalation in its many forms as it relates to the law enforcement profession

    Conception, optimisation, et vérification formelle de techniques de tolérance aux fautes pour circuits

    Get PDF
    Technology shrinking and voltage scaling increase the risk of fault occurrences in digital circuits. To address this challenge, engineers use fault-tolerance techniques to mask or, at least, to detect faults. These techniques are especially needed in safety critical domains (e.g., aerospace, medical, nuclear, etc.), where ensuring the circuit functionality and fault-tolerance is crucial. However, the verification of functional and fault-tolerance properties is a complex problem that cannot be solved with simulation-based methodologies due to the need to check a huge number of executions and fault occurrence scenarios. The optimization of the overheads imposed by fault-tolerance techniques also requires the proof that the circuit keeps its fault-tolerance properties after the optimization.In this work, we propose a verification-based optimization of existing fault-tolerance techniques as well as the design of new techniques and their formal verification using theorem proving. We first investigate how some majority voters can be removed from Triple-Modular Redundant (TMR) circuits without violating their fault-tolerance properties. The developed methodology clarifies how to take into account circuit native error-masking capabilities that may exist due to the structure of the combinational part or due to the way the circuit is used and communicates with the surrounding device.Second, we propose a family of time-redundant fault-tolerance techniques as automatic circuit transformations. They require less hardware resources than TMR alternatives and could be easily integrated in EDA tools. The transformations are based on the novel idea of dynamic time redundancy that allows the redundancy level to be changed "on-the-fly" without interrupting the computation. Therefore, time-redundancy can be used only in critical situations (e.g., above Earth poles where the radiation level is increased), during the processing of crucial data (e.g., the encryption of selected data), or during critical processes (e.g., a satellite computer reboot).Third, merging dynamic time redundancy with a micro-checkpointing mechanism, we have created a double-time redundancy transformation capable of masking transient faults. Our technique makes the recovery procedure transparent and the circuit input/output behavior remains unchanged even under faults. Due to the complexity of that method and the need to provide full assurance of its fault-tolerance capabilities, we have formally certified the technique using the Coq proof assistant. The developed proof methodology can be applied to certify other fault-tolerance techniques implemented through circuit transformations at the netlist level.La miniaturisation de la gravure et l'ajustement dynamique du voltage augmentent le risque de fautes dans les circuits intĂ©grĂ©s. Pour pallier cet inconvĂ©nient, les ingĂ©nieurs utilisent des techniques de tolĂ©rance aux fautes pour masquer ou, au moins, dĂ©tecter les fautes. Ces techniques sont particuliĂšrement utilisĂ©es dans les domaines critiques (aĂ©rospatial, mĂ©dical, nuclĂ©aire, etc.) oĂč les garanties de bon fonctionnement des circuits et leurs tolĂ©rance aux fautes sont cruciales. Cependant, la vĂ©rification de propriĂ©tĂ©s fonctionnelles et de tolĂ©rance aux fautes est un problĂšme complexe qui ne peut ĂȘtre rĂ©solu par simulation en raison du grand nombre d'exĂ©cutions possibles et de scĂ©narios d'occurrence des fautes. De mĂȘme, l'optimisation des surcoĂ»ts matĂ©riels ou temporels imposĂ©s par ces techniques demande de garantir que le circuit conserve ses propriĂ©tĂ©s de tolĂ©rance aux fautes aprĂšs optimisation.Dans cette thĂšse, nous dĂ©crivons une optimisation de techniques de tolĂ©rance aux fautes classiques basĂ©e sur des analyses statiques, ainsi que de nouvelles techniques basĂ©es sur la redondance temporelle. Nous prĂ©sentons comment leur correction peut ĂȘtre vĂ©rifiĂ©e formellement Ă  l'aide d'un assistant de preuves.Nous Ă©tudions d'abord comment certains voteurs majoritaires peuvent ĂȘtre supprimĂ©s des circuits basĂ©s sur la redondance matĂ©rielle triple (TMR) sans violer leurs propriĂ©tĂ©s de tolĂ©rance. La mĂ©thodologie dĂ©veloppĂ©e prend en compte les particularitĂ©s des circuits (par ex. masquage logique d'erreurs) et des entrĂ©es/sorties pour optimiser la technique TMR.DeuxiĂšmement, nous proposons une famille de techniques utilisant la redondance temporelle comme des transformations automatiques de circuits. Elles demandent moins de ressources matĂ©rielles que TMR et peuvent ĂȘtre facilement intĂ©grĂ©s dans les outils de CAO. Les transformations sont basĂ©es sur une nouvelle idĂ©e de redondance temporelle dynamique qui permet de modifier le niveau de redondance «à la volĂ©e» sans interrompre le calcul. Le niveau de redondance peut ĂȘtre augmentĂ© uniquement dans les situations critiques (par exemple, au-dessus des pĂŽles oĂč le niveau de rayonnement est Ă©levĂ©), lors du traitement de donnĂ©es cruciales (par exemple, le cryptage de donnĂ©es sensibles), ou pendant des processus critiques (par exemple, le redĂ©marrage de l'ordinateur d'un satellite).TroisiĂšmement, en associant la redondance temporelle dynamique avec un mĂ©canisme de micro-points de reprise, nous proposons une transformation avec redondance temporelle double capable de masquer les fautes transitoires. La procĂ©dure de recouvrement est transparente et le comportement entrĂ©e/sortie du circuit reste identique mĂȘme lors d'occurrences de fautes. En raison de la complexitĂ© de cette mĂ©thode, la garantie totale de sa correction a nĂ©cessitĂ© une certification formelle en utilisant l'assistant de preuves Coq. La mĂ©thodologie dĂ©veloppĂ©e peut ĂȘtre appliquĂ©e pour certifier d'autres techniques de tolĂ©rance aux fautes exprimĂ©es comme des transformations de circuits

    State, capital and migrant labour in Zambezia, Mozambique : a study of the labour force of the Sena Sugar Estates Limited.

    Get PDF
    SIGLEAvailable from British Library Document Supply Centre- DSC:D33786/81 / BLDSC - British Library Document Supply CentreGBUnited Kingdo
    • 

    corecore