DSA-aware multiple patterning for the manufacturing of vias: Connections to graph coloring problems, IP formulations, and numerical experiments

In this paper, we investigate the manufacturing of vias in integrated circuits with a new technology combining lithography and Directed Self Assembly (DSA). Optimizing the production time and costs in this new process entails minimizing the number of lithography steps, which constitutes a generalization of graph coloring. We develop integer programming formulations for several variants of interest in the industry, and then study the computational performance of our formulations on true industrial instances. We show that the best integer programming formulation achieves good computational performance, and indicate potential directions to further speed-up computational time and develop exact approaches feasible for production

Standard cell optimization and physical design in advanced technology nodes

Integrated circuits (ICs) are at the heart of modern electronics, which rely heavily on the state-of-the-art semiconductor manufacturing technology. The key to pushing forward semiconductor technology is IC feature-size miniaturization. However, this brings ever-increasing design complexities and manufacturing challenges to the $340 billion semiconductor industry. The manufacturing of two-dimensional layout on high-density metal layers depends on complex design-for-manufacturing techniques and sophisticated empirical optimizations, which introduces huge amounts of turnaround time and yield loss in advanced technology nodes. Our study reveals that unidirectional layout design can significantly reduce the manufacturing complexities and improve the yield, which is becoming increasingly adopted in semiconductor industry [61, 89]. The lithography printing of unidirectional layout can be tightly controlled using advanced patterning techniques, such as self-aligned double and quadruple patterning. Despite the manufacturing benefits, unidirectional layout leads to more restrictive solution space and brings significant impacts on the IC design automation ow for routing closure. Notably, unidirectional routing limits the standard cell pin accessibility, which further exacerbates the resource competitions during routing. Moreover, for post-routing optimization, traditional redundant-via insertion has become obsolete under unidirectional routing style, which makes the yield enhancement task extremely challenging. Regardless of complex multiple patterning and design-for-manufacturing approaches, mask optimization through resolution enhancement techniques remains as the key strategy to improve the yield of the semiconductor manufacturing processes. Among them, Sub-Resolution Assist Feature (SRAF) generation is a very important method to improve lithographic process windows. Model-based SRAF generation has been widely used to achieve high accuracy but it is time-consuming and hard to obtain consistent SRAFs. This dissertation proposes novel CAD algorithms and methodologies for standard cell optimization and physical design in advanced technology nodes, which ultimately reduces the design cycle and manufacturing cost of IC design. First, a standard cell pin access optimization engine is proposed to evaluate the pin accessibility of a given standard cell library. We further propose novel pin access planning techniques and concurrent pin access optimizations to efficiently resolve the routing resource competitions, which generates much better routing solutions than state-of-the-art, manufacturing-friendly routers. To systematically improve the manufacturing yield in the post-routing stage, a global optimization engine has been introduced for redundant local-loop insertion considering advanced manufacturing constraints. Finally, we propose the first machine learning-based framework for fast yet consistent SRAF generation with the high quality of results.Electrical and Computer Engineerin

Nasics: A `Fabric-Centric\u27 Approach Towards Integrated Nanosystems

This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first\u27 mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric\u27 mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below

The Fabrication and Applications of Protein Patterns Produced Via Particle Lithography

A novel particle lithography technique with the ability to pattern protein in hexagonal dot arrays was developed. The patterning method consists of a simple three-step procedure: (1) formation of a close-packed polystyrene microsphere monolayer, (2) grafting of a protein-resistant layer of poly(ethylene glycol) (PEG), and (3)selective adsorption of protein into the resulting PEG holes. The diameter and center-to-center spacing of the patterned features was varied simultaneously by changing the diameter of the spheres used in the lithographic mask or independently using a simple heating modification. A combination of the original and modified procedures was used to produce patterns of protein dots with diameters of 450 nm - 9 ìm and center-to-center spacings of 2 - 10 ìm. To demonstrate the applicability of the particle lithography technique, a fluorescent-based immunoassay was created using quantum dot bioconjugates (QDBCs). The millions of protein dot features per patterned substrate served as redundant sampling points that produced a subpicomolar detection limit. Finally, the QDBC patterns were also used to investigate the differences between neutrophil spreading on patterned and homogenously coated anti-PSGL-1 (PL1) surfaces

Algorithms for DFM in electronic design automation

As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit of physics at the expense of design flexibility. On the other hand, IC designs inevitably becomes more complex to meet the increasing demand of computational power. To close this gap, design for manufacturing (DFM) becomes the key to enable an easy and low-cost IC fabrication. Therefore, efficient electronic design automation (EDA) algorithms must be developed for DFM to address the design constraints and help the designers to better facilitate the manufacture process. As the core of manufacturing ICs, conventional lithography systems (193i) reach their limit for the 22 nm technology node and beyond. Consequently, several advanced lithography techniques are proposed, such as multiple patterning lithography (MPL), extreme ultra-violet lithography (EUV), electron beam (E-beam), and block copolymer directed self-assembly (DSA); however, DFM algorithms are essential for them to achieve better printability of a design. In this dissertation, we focus on analyzing the compatibility of designs and various advanced lithography techniques, and develop efficient algorithms to enable the manufacturing. We first explore E-Beam, one of the promising candidates for IC fabrication beyond the 10 nm technology node. To address its low throughput issue, the character projection technique has been proposed, and its stencil planning can be optimized with an awareness of overlapping characters. 2D stencil planning is proved NP-Hard. With the assumption of standard cells, the 2D problem can be partitioned into 1D row ordering subproblems; however, it is also considered hard, and no efficient optimal solution has been provided so far. We propose a polynomial time optimal algorithm to solve the 1D row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Technical proofs and experimental results verify that our algorithm is efficient and indeed optimal. As the most popular and practical lithography technique, MPL utilizes multiple exposures to print a single layout and thus allows placement of features within the minimum distance. Therefore, a feasible decomposition of the layout is a must to adopt MPL, and it is usually formulated as a graph k-coloring problem, which is computationally difficult for k > 2. We study the k-colorability of rectangular and diagonal grid graphs as induced subgraphs of a rectangular or diagonal grid respectively, since it has direct applications in printing contact/via layouts. It remains an open question on how hard it is to color grid graphs due to their regularity and sparsity. In this dissertation, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm for those graphs and conduct experiments to verify its performance and effectiveness. Besides, we also develop an efficient algorithm for model based MPL, because it is more expensive but accurate than the rule based decomposition. As one of the alternative lithography techniques, block copolymer directed self-assembly (DSA) is studied. It has emerged as a low-cost, high- throughput option in the pursuit of alternatives to traditional optical lithography. However, issues of defectivity have hampered DSA’s viability for large-scale patterning. Recent studies have shown the copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density has been demonstrated. In this dissertation, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. We also apply our knowledge in coloring grid graphs to the problem of group-and-coloring in DSA-MPL hybrid lithography. We derive a solution to group-3-coloring and prove the NP-completeness of grouping-2-coloring

Organic lasers: recent developments on materials, device geometries, and fabrication techniques

MCG acknowledges financial support through the ERC Starting Grant ABLASE (640012) and the European Union Marie Curie Career Integration Grant (PCIG12-GA-2012-334407). AJCK acknowledges financial support by the German Federal Ministry for Education and Research through a NanoMatFutur research group (BMBF grant no. 13N13522).Organic dyes have been used as gain medium for lasers since the 1960s, long before the advent of today’s organic electronic devices. Organic gain materials are highly attractive for lasing due to their chemical tunability and large stimulated emission cross section. While the traditional dye laser has been largely replaced by solid-state lasers, a number of new and miniaturized organic lasers have emerged that hold great potential for lab-on-chip applications, biointegration, low-cost sensing and related areas, which benefit from the unique properties of organic gain materials. On the fundamental level, these include high exciton binding energy, low refractive index (compared to inorganic semiconductors), and ease of spectral and chemical tuning. On a technological level, mechanical flexibility and compatibility with simple processing techniques such as printing, roll-to-roll, self-assembly, and soft-lithography are most relevant. Here, the authors provide a comprehensive review of the developments in the field over the past decade, discussing recent advances in organic gain materials, which are today often based on solid-state organic semiconductors, as well as optical feedback structures, and device fabrication. Recent efforts toward continuous wave operation and electrical pumping of solid-state organic lasers are reviewed, and new device concepts and emerging applications are summarized.PostprintPeer reviewe

Actuatable Membranes based on Polypyrrole-Coated Vertically Aligned Nanostructures

Nanoporous membranes are an enabling technology in a wide variety of applications because of their ability to efficiently and selectively separate molecules. A great deal of effort is concentrated on developing methods of externally controlling membrane selectivity and on integrating the membranes within multi-scale systems. In this dissertation, synthetic nanoporous membranes that fit the described needs are constructed from vertically aligned nanostructures. Vertically aligned carbon nanofibers and anisotropically etched silicon posts are aligned perpendicular to the substrate and act as obstacles to material flow parallel to the surface. The distances between the outer edges of the nanostructures define the pores of the membranes. Transport through the membranes is controlled by physically selecting species as they pass between the vertically aligned nanostructures. Membrane properties such as permeability and porosity are specified by defining the spatial locations of the membrane components. Subsequent physical and chemical modification of the nanostructures enables further tuning of pore sizes and opens up new methods to controllably modulate the permeability of the membranes. In this dissertation, permeability is externally controlled by electrochemical actuation of the conductive polymer, polypyrrole. Vertically aligned membrane components are coated with the actuatable polymer. Upon electrochemical reduction, the polypyrrole coatings swell in volume, increasing the diameters of the membrane components and decreasing the pore sizes of the membranes. Modulating the physical size of the membrane pores enables size selective transport of species and gating of the nanoscale pores