Gbit/second lossless data compression hardware

This thesis investigates how to improve the performance of lossless data compression hardware as a tool to reduce the cost per bit stored in a computer system or transmitted over a communication network. Lossless data compression allows the exact reconstruction of the original data after decompression. Its deployment in some high-bandwidth applications has been hampered due to performance limitations in the compressing hardware that needs to match the performance of the original system to avoid becoming a bottleneck. Advancing the area of lossless data compression hardware, hence, offers a valid motivation with the potential of doubling the performance of the system that incorporates it with minimum investment. This work starts by presenting an analysis of current compression methods with the objective of identifying the factors that limit performance and also the factors that increase it. [Continues.

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

A wearable heart monitor at the ear using ballistocardiogram (BCG) and electrocardiogram (ECG) with a nanowatt ECG heartbeat detection circuit

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 132-137).This work presents a wearable heart monitor at the ear that uses the ballistocardiogram (BCG) and the electrocardiogram (ECG) to extract heart rate, stroke volume, and pre-ejection period (PEP) for the application of continuous heart monitoring. Being a natural anchoring point, the ear is demonstrated as a viable location for the integrated sensing of physiological signals. The source of periodic head movements is identified as a type of BCG, which is measured using an accelerometer. The head BCG's principal peaks (J-waves) are synchronized to heartbeats. Ensemble averaging is used to obtain consistent J-wave amplitudes, which are related to stroke volume. The ECG is sensed locally near the ear using a single-lead configuration. When the BCG and the ECG are used together, an electromechanical duration called the RJ interval can be obtained. Because both head BCG and ECG have low signal-to-noise ratios, cross-correlation is used to statistically extract the RJ interval. The ear-worn device is wirelessly connected to a computer for real time data recording. A clinical test involving hemodynamic maneuvers is performed on 13 subjects. The results demonstrate a linear relationship between the J-wave amplitude and stroke volume, and a linear relationship between the RJ interval and PEP. While the clinical device uses commercial components, a custom integrated circuit for ECG heartbeat detection is designed with the goal of reducing power consumption and device size. With 58nW of power consumption, the ECG circuit replaces the traditional instrumentation amplifier, analog-to-digital converter, and signal processor with a single chip solution. The circuit demonstrates a topology that takes advantage of the ECG's characteristics to extract R-wave timings at the chest and the ear in the presence of baseline drift, muscle artifact, and signal clipping.by David Da He.Ph.D

Supplier research and development : how Japanese multinational companies are innovating in their global networks

Includes bibliographical references (p. 41-43).Christopher J. Voisey

A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and performing the inverse Haar wavelet transform, returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation. A reduction of RAM accesses was realized and a tradeoff between states and duplication of components for parallel operation were key to the performance gains. Almost half of the external RAM accesses were removed from the FPGA design by incorporating an internal register file. This reduction reduced the number of states needed to process an image increasing the image frame rate by 13% and decreased I/O traffic on the bus by 47%. Adding control lines to the ALU components, thus eliminating unnecessary switching of combination logic blocks, further reduced power requirements. The 22 mm2 ASIC consumes an estimated 430 mW of power when operating at the maximum frequency of 17 MHz

High-level synthesis for FPGAs: From prototyping to deployment

Abstract-Escalating System-on-Chip design complexity is pushing the design community to raise the level of abstraction beyond RTL. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for FPGA designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR)