A New Low Complexity Uniform Filter Bank Based on the Improved Coefficient Decimation Method

In this paper, we propose a new uniform filter bank (FB) based on the improved coefficient decimation method (ICDM). In the proposed FB’s design, the ICDM is used to obtain different multi-band frequency responses using a single lowpass prototype filter. The desired subbands are individually obtained from these multi-band frequency responses by using low order frequency response masking filters and their corresponding ICDM output frequency responses. We show that the proposed FB is a very low complexity alternative to the other FBs in literature, especially the widely used discrete Fourier transform based FB (DFTFB) and the CDM based FB (CDFB). The proposed FB can have a higher number of subbands with twice the center frequency resolution when compared with the CDFB and DFTFB. Design example and implementation results show that our FB achieves 86.59% and 58.84% reductions in resource utilizations and 76.95% and 47.09% reductions in power consumptions when compared with the DFTFB and CDFB respectively

Channelization for Multi-Standard Software-Defined Radio Base Stations

As the number of radio standards increase and spectrum resources come under more pressure, it becomes ever less efficient to reserve bands of spectrum for exclusive use by a single radio standard. Therefore, this work focuses on channelization structures compatible with spectrum sharing among multiple wireless standards and dynamic spectrum allocation in particular. A channelizer extracts independent communication channels from a wideband signal, and is one of the most computationally expensive components in a communications receiver. This work specifically focuses on non-uniform channelizers suitable for multi-standard Software-Defined Radio (SDR) base stations in general and public mobile radio base stations in particular. A comprehensive evaluation of non-uniform channelizers (existing and developed during the course of this work) shows that parallel and recombined variants of the Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB) represent the best trade-off between computational load and flexibility for dynamic spectrum allocation. Nevertheless, for base station applications (with many channels) very high filter orders may be required, making the channelizers difficult to physically implement. To mitigate this problem, multi-stage filtering techniques are applied to the GDFT-FB. It is shown that these multi-stage designs can significantly reduce the filter orders and number of operations required by the GDFT-FB. An alternative approach, applying frequency response masking techniques to the GDFT-FB prototype filter design, leads to even bigger reductions in the number of coefficients, but computational load is only reduced for oversampled configurations and then not as much as for the multi-stage designs. Both techniques render the implementation of GDFT-FB based non-uniform channelizers more practical. Finally, channelization solutions for some real-world spectrum sharing use cases are developed before some final physical implementation issues are considered

Efficient Multi-Standard Software Defined Radio receivers implementation using Frequency response masking Naveena P and Nithya S

The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The polyphase channelizer has the advantage that the channel filter can be adjusted to better approximate the ideal magnitude response.Hanning Window functions can also be used to improve the side lobe response without any of the performance penalties associated with the FFT channelizer. The proposed FB offers reconfigurability at the architectural level and at the channel filter level and is capable of extracting channels of nonuniform bandwidths corresponding to multiple wireless communication standard from the digitized wideband input signal

A power and time efficient radio architecture for LDACS1 air-to-ground communication

L-band Digital Aeronautical Communication System (LDACS) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. The standard places stringent requirements on the communication channels to allow them to coexist with critical L-band systems, requiring complex processing and filters in baseband. Approaches based on cognitive radio are also proposed since this allows tremendous increase in communication capacity and spectral efficiency. This requires high computational capability in airborne vehicles that can perform the complex filtering and masking, along with tasks associated with cognitive radio systems like spectrum sensing and baseband adaptation, while consuming very less power. This paper proposes a radio architecture based on new generation FPGAs that offers advanced capabilities like partial reconfiguration. The proposed architecture allows non-concurrent baseband modules to be dynamically loaded only when they are required, resulting in improved energy efficiency, without sacrificing performance. We evaluate the case of non-concurrent spectrum sensing logic and transmission filters on our cognitive radio platform based on Xilinx Zynq, and show that our approach results in 28.3% reduction in DSP utilisation leading to lower energy consumption at run-time

FPGA based Uniform Channelizer Implementation

Channelizers are widely used in modern digital communication systems. Advanced uniform multirate channelization have been theoretically proved to be capable of reducing the computational load, with a better performance. Therefore, in this thesis, we implement these designs on a FPGA board for the sake of the comprehensive evaluation of resource usage, performance and frequency response. The uniform filter-banks are one of the most essential unit in channelization. The Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB), as an important variant of basic a DFT-FB, has been implemented in FPGA and demonstrated with a better computational saving rather than traditional schemes. Moreover the oversampling version is demonstrated to have a better frequency response with an acceptable amount of extra resources. On the other hand, frequency response masking (FRM) techniques is able to reduce the number of coefficients. Therefore, the full FRM GDFT-FB and alternative narrowband FRM GDFT-FB are both implemented in FPGA platform, in order to achieve a better performance and hardware efficiency

Non-Uniform Channelization Methods for Next Generation SDR PMR Base Stations

Channelization in multi-standard Software-Defined Radio base stations presents a significant challenge. In this paper, two different channelization structures designed for a multi-standard SDR base station are studied. As a basis for comparing their computational efficiency and reconfigurability, both are applied to a specific case study of a TETRA and TEDS standards base station. Uniform narrow band spectrum division followed by channel recombination demonstrates greater flexibility than a non-uniform parallel spectrum division alternative. However, computational advantages between both structures depend on the channel allocation patterns considered

Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems

Recently proposed quantum systems use frequency multiplexed qubit technology for readout electronics rather than analog circuitry, to increase cost effectiveness of the system. In order to restore individual channels for further processing, these systems require a demultiplexing or channelization approach which can process high data rates with low latency and uses few hardware resources. In this paper, a low latency, adaptable, FPGA-based channelizer using the Polyphase Filter Bank (PFB) signal processing algorithm is presented. As only a single prototype lowpass filter needs to be designed to process all channels, PFBs can be easily adapted to different requirements and further allow for simplified filter design. Due to reutilization of the same filter for each channel they also reduce hardware resource utilization when compared to the traditional Digital Down Conversion approach. The realized system architecture is extensively generic, allowing the user to select from different numbers of channels, sample bit widths and throughput specifications. For a test setup using a 28 coefficient transpose filter and 4 output channels, the proposed architecture yields a throughput of 12.8 Gb/s with a latency of 7 clock cycles