Design of a semi-automatic transmission

Design of a semi-automatic four-speed transmission for automotive engines with moderate horsepower is described. The basic configuration consists of main and countershafts and five pairs of constant-mesh gears. Engine torque is transmitted through an input gear pair to the countershaft, and finally to the output shaft through a selected output gear pair. Selection is accomplished by engaging one of five hydraulically operated clutches located on the countershaft. Engagement fixes the desired gear to the countershaft and engine torque is then transmitted to the mating gear, which is fixed to the output shaft. Fourth speed is obtained by coupling the input shaft directly to the output shaft through a sixth clutch. Design of clutches, gears, shafts, supply pump and control valves is analyzed in detail. Requirements for a master clutch, for use during acceleration from rest, are summarized --Abstract, page ii

FPGA-based DOCSIS upstream demodulation

In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced

Metastability-containing circuits, parallel distance problems, and terrain guarding

We study three problems. The first is the phenomenon of metastability in digital circuits. This is a state of bistable storage elements, such as registers, that is neither logical 0 nor 1 and breaks the abstraction of Boolean logic. We propose a time- and value-discrete model for metastability in digital circuits and show that it reflects relevant physical properties. Further, we propose the fundamentally new approach of using logical masking to perform meaningful computations despite the presence of metastable upsets and analyze what functions can be computed in our model. Additionally, we show that circuits with masking registers grow computationally more powerful with each available clock cycle. The second topic are parallel algorithms, based on an algebraic abstraction of the Moore-Bellman-Ford algorithm, for solving various distance problems. Our focus are distance approximations that obey the triangle inequality while at the same time achieving polylogarithmic depth and low work. Finally, we study the continuous Terrain Guarding Problem. We show that it has a rational discretization with a quadratic number of guard candidates, establish its membership in NP and the existence of a PTAS, and present an efficient implementation of a solver.Wir betrachten drei Probleme, zunächst das Phänomen von Metastabilität in digitalen Schaltungen. Dabei geht es um einen Zustand in bistabilen Speicherelementen, z.B. Registern, welcher weder logisch 0 noch 1 entspricht und die Abstraktion Boolescher Logik unterwandert. Wir präsentieren ein zeit- und wertdiskretes Modell für Metastabilität in digitalen Schaltungen und zeigen, dass es relevante physikalische Eigenschaften abbildet. Des Weiteren präsentieren wir den grundlegend neuen Ansatz, trotz auftretender Metastabilität mit Hilfe von logischem Maskieren sinnvolle Berechnungen durchzuführen und bestimmen, welche Funktionen in unserem Modell berechenbar sind. Darüber hinaus zeigen wir, dass durch Maskingregister in zusätzlichen Taktzyklen mehr Funktionen berechenbar werden. Das zweite Thema sind parallele Algorithmen die, basierend auf einer Algebraisierung des Moore-Bellman-Ford-Algorithmus, diverse Distanzprobleme lösen. Der Fokus liegt auf Distanzapproximationen unter Einhaltung der Dreiecksungleichung bei polylogarithmischer Tiefe und niedriger Arbeit. Abschließend betrachten wir das kontinuierliche Terrain Guarding Problem. Wir zeigen, dass es eine rationale Diskretisierung mit einer quadratischen Anzahl von Wächterpositionen erlaubt, folgern dass es in NP liegt und ein PTAS existiert und präsentieren eine effiziente Implementierung, die es löst

Accurate spectral test algorithms with relaxed instrumentation requirements

Spectral testing is widely used to test the dynamic linearity performance of Analog-to-Digital Converters (ADC) and waveform generators. Dynamic specifications for ADCs are very important in high speed applications such as digital communications, ultrasound imaging and instrumentation. With improvements in the performance of ADCs, it is becoming an expensive and challenging task to perform spectral testing using standard methods due to the requirement that the test instrumentation environment must satisfy several stringent conditions. In order to address these challenges and to decrease the test cost, in this dissertation, three new algorithms are proposed to perform accurate spectral testing of ADCs by relaxing three necessary conditions required for standard spectral testing methods. The testing is done using uniformly sampled points. The first method introduces a new fundamental identification and replacement (FIRE) method, which eliminates the requirement of coherent sampling when using the DFT for testing the spectral response of an ADC. The robustness and accuracy of the proposed FIRE method is verified using simulation and measurement results obtained with non-coherently sampled data. The second method, namely, the Fundamental Estimation, Removal and Residue Interpolation (FERARI) method, is proposed to eliminate the requirement of precise control over amplitude and frequency of the input signal to the ADC. This method can be used when the ADC output is both non-coherently sampled and clipped. Simulation and measurement results using the FERARI method with non-coherently sampled and clipped outputs of the ADC are used to validate this approach. A third spectral test method is proposed that simultaneously relaxes the conditions of using a spectrally pure input source and coherent sampling. Using this method, the spectral characteristics of a high resolution ADC can be accurately tested using a non-coherently sampled output obtained with a sinusoidal input signal that has significant and unknown levels of nonlinear distortion. Simulation results are presented that show the accuracy and robustness of the proposed method. Finally, the issue of metastability in comparators and Successive Approximation Register (SAR) ADCs is analyzed. The analysis of probability of metastability in SAR ADCs with and without using metastable detection circuits is provided. Using this analysis, it is shown that as the frequency of sampling clock increases, using a metastable detection circuit decreases the probability of metastability in SAR ADC

Data systems elements technology assessment and system specifications, issue no. 2

The ability to satisfy the objectives of future NASA Office of Applications programs is dependent on technology advances in a number of areas of data systems. The hardware and software technology of end-to-end systems (data processing elements through ground processing, dissemination, and presentation) are examined in terms of state of the art, trends, and projected developments in the 1980 to 1985 timeframe. Capability is considered in terms of elements that are either commercially available or that can be implemented from commercially available components with minimal development

A Simple Optimum-Time FSSP Algorithm for Multi-Dimensional Cellular Automata

The firing squad synchronization problem (FSSP) on cellular automata has been studied extensively for more than forty years, and a rich variety of synchronization algorithms have been proposed for not only one-dimensional arrays but two-dimensional arrays. In the present paper, we propose a simple recursive-halving based optimum-time synchronization algorithm that can synchronize any rectangle arrays of size m*n with a general at one corner in m+n+max(m, n)-3 steps. The algorithm is a natural expansion of the well-known FSSP algorithm proposed by Balzer [1967], Gerken [1987], and Waksman [1966] and it can be easily expanded to three-dimensional arrays, even to multi-dimensional arrays with a general at any position of the array.Comment: In Proceedings AUTOMATA&JAC 2012, arXiv:1208.249

MIDAS, prototype Multivariate Interactive Digital Analysis System for large area earth resources surveys. Volume 1: System description

A third-generation, fast, low cost, multispectral recognition system (MIDAS) able to keep pace with the large quantity and high rates of data acquisition from large regions with present and projected sensots is described. The program can process a complete ERTS frame in forty seconds and provide a color map of sixteen constituent categories in a few minutes. A principle objective of the MIDAS program is to provide a system well interfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughput. The hardware and software generated in the overall program is described. The system contains a midi-computer to control the various high speed processing elements in the data path, a preprocessor to condition data, and a classifier which implements an all digital prototype multivariate Gaussian maximum likelihood or a Bayesian decision algorithm. Sufficient software was developed to perform signature extraction, control the preprocessor, compute classifier coefficients, control the classifier operation, operate the color display and printer, and diagnose operation

Cross-Correlator Implementations Enabling Aperture Synthesis for Geostationary-Based Remote Sensing

An ever-increasing demand for weather prediction and high climate modelling accuracy drives the need for better atmospheric data collection. These demands include better spatial and temporal coverage of mainly humidity and temperature distributions in the atmosphere. A new type of remote sensing satellite technology is emerging, originating in the field of radio astronomy where telescope aperture upscaling could not keep up with the increasing demand for higher resolution. Aperture synthesis imaging takes an array of receivers and emulates apertures extending way beyond what is possible with any single antenna. In the field of Earth remote sensing, the same idea could be used to construct satellites observing in the microwave region at a high resolution with foldable antenna arrays. If placed in a geostationary orbit, these could produce images with high temporal resolution, however, such altitudes make the resolution requirement and, hence, signal processing very demanding. The relentless development in miniaturization of integrated circuits has in recent years made the concept of high resolution aperture synthesis imaging aboard a satellite platform viable.The work presented in this thesis addresses the challenge of performing the vital signal processing required aboard an aperture synthesis imager; namely the cross-correlation. A number of factors make the application challenging; the very restrictive power budgets of satellites, the immense amount of signal processing required for larger arrays, and the environmental aspects of in-space operation. The design, fabrication and evaluation of two cross-correlator application-specific integrated circuits (ASICs), one analog-to-digital converter (ADC) ASIC and one complete cross-correlator back-end is presented. Design concepts such as clocking schemes, data routing and reconfigurable accuracy for the cross-correlators and offset compensation and interfacing of the ADCs are explained. The underlying reasons for design choices as well as ASIC design and testing methodologies are described. The ASICs are put into their proper context as part of an interferometer system, and some different cross-correlator back-end architectures are explored.The result from this work is a very power-efficient, high-performance way of constructing cross-correlators which clearly demonstrates the viability of space-borne microwave imaging interferometer back-ends