Time-Recovering PCI-AER interface for Bio-inspired Spiking Systems

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate ‘events’ according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) inject a sequence of events at some point of the AER structure. This is necessary for testing and debugging complex AER systems. This paper presents a PCI to AER interface, that dispatches a sequence of events received from the PCI bus with embedded timing information to establish when each event will be delivered. A set of specialized states machines has been introduced to recovery the possible time delays introduced by the asynchronous AER bus. On the input channel, the interface capture events assigning a timestamp and delivers them through the PCI bus to MATLAB applications. It has been implemented in real time hardware using VHDL and it has been tested in a PCI-AER board, developed by authors, that includes a Spartan II 200 FPGA. The demonstration hardware is currently capable to send and receive events at a peak rate of 8,3 Mev/sec, and a typical rate of 1 Mev/sec.European Commission IST-2001-34124Ministerio de Educación y Ciencia TIC-2000-0406-P

Out-of-step Protection Using Energy Equilibrium Criterion in the Time Domain

Disturbances in power systems are common and they result in electromechanical oscillations called power swing. The power swings could be severe and it may lead to loss of synchronism among the interconnected generators. This is referred to as out-of-step condition. The voltage and current swings during an out-of-step condition damage power system equipments and also cause unwanted operations of various protective devices. The protection systems require an effective algorithm for fast and accurate detection of out-of-step condition. This research is focused on the development of a simple and effective out-of-step relay capable of detecting out-of-step condition in a complex power system. To achieve this, the research has gone through four distinct stages: development of an algorithm, simulation, hardware implementation and its testing. An out-of-step algorithm is proposed based on equal area criterion in time domain. The equal area criterion in time domain is obtained by modifying the traditional equal area criterion in power angle domain. A single machine infinite bus system, a two machine infinite bus system and a three machine infinite bus system and a 17-bus multiple machines system are used as case studies and are modeled using simulation tool(PSCAD™). To test the effectiveness of the proposed algorithm, various out-of-step conditions are simulated by applying disturbances at various locations in the above chosen power system configurations. For hardware implementation and testing of the algorithm, a digital signal processing board (ADSP-BF533 from Analog Devices ™) is used. To test the performance of the developed digital relay in a closed loop, real time power system signals are necessary and therefore for this purpose, a Real Time Digital Simulator (RTDS™) available in the power research laboratory is used. The RTDS™ simulator mimics the actual power systems in real time. The signals required by the relays can be tapped from the RTDS™ and the signals coming from relay can be fed back into the RTDS™, which makes the closed loop testing of the digital relay possible. This research has yielded a simple out-of-step algorithm and unlike the other out-of-step detection techniques proposed in the literature does not need offline system studies to arrive at a solution.The developed digital out-of-step relay is capable of making decisions based only on the information available from its point of installation, thus it avoids the communication devices which is advantageous for the out-of-step protection of a complex power system. Finally, the simulation results show that the proposed algorithm can be applied to any power configurations and is faster compared to the conventional concentric rectangle schemes used in the literature

A Distributed Computing Architecture for Small Satellite and Multi-Spacecraft Missions

Distributed computing architectures offer numerous advantages in the development of complex devices and systems. This paper describes the design, implementation and testing of a distributed computing architecture for low-cost small satellite and multi-spacecraft missions. This system is composed of a network of PICmicro® microcontrollers linked together by an I2C serial data communication bus. The system also supports sensor and component integration via Dallas 1-wire and RS232 standards. A configuration control processor serves as the external gateway for communication to the ground and other satellites in the network; this processor runs a multitasking real-time operating system and an advanced production rule system for on-board autonomy. The data handling system allows for direct command and data routing between distinct hardware components and software tasks. This capability naturally extends to distributed control between spacecraft subsystems, between constellation satellites, and between the space and ground segments. This paper describes the technical design of the aforementioned features. It also reviews the use of this system as part of the two-satellite Emerald and QUEST university small satellite missions

Estimating Uncertainty of Bus Arrival Times and Passenger Occupancies

Travel time reliability and the availability of seating and boarding space are important indicators of bus service quality and strongly influence users’ satisfaction and attitudes towards bus transit systems. With Automated Vehicle Location (AVL) and Automated Passenger Counter (APC) units becoming common on buses, some agencies have begun to provide real-time bus location and passenger occupancy information as a means to improve perceived transit reliability. Travel time prediction models have also been established based on AVL and APC data. However, existing travel time prediction models fail to provide an indication of the uncertainty associated with these estimates. This can cause a false sense of precision, which can lead to experiences associated with unreliable service. Furthermore, no existing models are available to predict individual bus occupancies at downstream stops to help travelers understand if there will be space available to board. The purpose of this project was to develop modeling frameworks to predict travel times (and associated uncertainties) as well as individual bus passenger occupancies. For travel times, accelerated failure-time survival models were used to predict the entire distribution of travel times expected. The survival models were found to be just as accurate as models developed using traditional linear regression techniques. However, the survival models were found to have smaller variances associated with predictions. For passenger occupancies, linear and count regression models were compared. The linear regression models were found to outperform count regression models, perhaps due to the additive nature of the passenger boarding process. Various modeling frameworks were tested and the best frameworks were identified for predictions at near stops (within five stops downstream) and far stops (further than eight stops). Overall, these results can be integrated into existing real-time transit information systems to improve the quality of information provided to passengers

The European bus system of the future: Research and innovation

The development of a new generation of bus systems was the goal of the European Bus System of the Future (EBSF) project, funded by the European Commission within the 7th Framework Program. To accomplish this, a series of very different innovative solutions for buses (such as new vehicle layouts, advanced remote maintenance systems, improved on-board communication systems, more performing bus stops and eco-efficient engines) were simultaneously tested in seven Use Cases (UCs) in Europe (Bremerhaven, Brunoy, Budapest, Gothenburg, Madrid, Rome and Rouen). All the tested measures had to increase the attractiveness and improve the image of the mode. The efficiency of all of them was assessed as well as their transferability to other European contexts. The paper describes the tested solutions and focuses on the assessment methodology, the main results achieved and the drivers and barriers for the transfer of such solutions across Europe

Test Infrastructure for Address-Event-Representation Communications

Address-Event-Representation (AER) is a communication protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them in real time, while performing some processing. To develop and test AER based systems it is convenient to have a set of instruments that would allow to: generate AER streams, monitor the output produced by neural chips and modify the spike stream produced by an emitting chip to adapt it to the requirements of the receiving elements. In this paper we present a set of tools that implement these functions developed in the CAVIAR EU project.Unión Europea IST-2001-34124 (CAVIAR)Ministerio de Ciencia y Tecnología TIC-2003-08164-C03-0

Functional Verification of Power Electronic Systems

This project is the final work of the degree in Industrial Electronics and Automatic Engineering. It has global concepts of electronics but it focuses in power electronic systems. There is a need for reliable testing systems to ensure the good functionality of power electronic systems. The constant evolution of this products requires the development of new testing techniques. This project aims to develop a new testing system to accomplish the functional verification of a new power electronic system manufactured on a company that is in the power electronic sector . This test system consists on two test bed platforms, one to test the control part of the systems and the other one to test their functionality. A software to perform the test is also designed. Finally, the testing protocol is presented. This design is validated and then implemented on a buck converter and an inverter that are manufactured at the company. The results show that the test system is reliable and is capable of testing the functional verification of the two power electronic system successfully. In summary, this design can be introduced in the power electronic production process to test the two products ensuring their reliability in the market

LVDS Serial AER Link performance

Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows analysing a LVDS Serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The interface allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0

Build an app and they will come? Lessons learnt from trialling the GetThereBus app in rural communities

Acknowledgements The research described here was supported by the award made by the RCUK Digital Economy programme to the dot.rural Digital Economy Hub; award reference: EP/G066051/1.Peer reviewedPostprin