FPGA Implementation of Double Precision Floating Point Multiplier

High speed computation is the need of today’s generation of Processors.  To accomplish this major task,  many functions  are implemented  inside the hardware  of the processor rather than  having  software  computing  the  same  task. Majority of the operations which the processor executes are Arithmetic operations which are widely used in many applications that require heavy mathematical operations such as scientific calculations, image and signal processing. Especially in the field of signal processing, multiplication division operation is widely used in many applications. The major issue with these operations in hardware is that much iteration is required which results in slow operation while fast algorithms require complex computations within each cycle. The result of a Division operation results in a either  in Quotient  and  Remainder  or a Floating  point  number  which is the  major reason  to  make it  more complex than  Multiplication  operation

The Impact of the Multi-core Revolution on Signal Processing

This paper analyzes the influence of new multi- core and many-core architectures on Signal Processing. The article covers both the architectural design and the programming models of current general-purpose multi-core processors and graphics processors (GPU), with the goal of identifying their possibilities and impact on signal processing applications

Convergence of millimeter-wave and photonic interconnect systems for very-high-throughput digital communication applications

In the past, radio-frequency signals were commonly used for low-speed wireless electronic systems, and optical signals were used for multi-gigabit wired communication systems. However, as the emergence of new millimeter-wave technology introduces multi-gigabit transmission over a wireless radio-frequency channel, the borderline between radio-frequency and optical systems becomes blurred. As a result, there come ample opportunities to design and develop next-generation broadband systems to combine the advantages of these two technologies to overcome inherent limitations of various broadband end-to-end interconnect systems in signal generation, recovery, synchronization, and so on. For the transmission distances of a few centimeters to thousands of kilometers, the convergence of radio-frequency electronics and optics to build radio-over-fiber systems ushers in a new era of research for the upcoming very-high-throughput broadband services. Radio-over-fiber systems are believed to be the most promising solution to the backhaul transmission of the millimeter-wave wireless access networks, especially for the license-free, very-high-throughput 60-GHz band. Adopting radio-over-fiber systems in access or in-building networks can greatly extend the 60-GHz signal reach by using ultra-low loss optical fibers. However, such high frequency is difficult to generate in a straightforward way. In this dissertation, the novel techniques of homodyne and heterodyne optical-carrier suppressions for radio-over-fiber systems are investigated and various system architectures are designed to overcome these limitations of 60-GHz wireless access networks, bringing the popularization of multi-gigabit wireless networks to become closer to the reality. In addition to the advantages for the access networks, extremely high spectral efficiency, which is the most important parameter for long-haul networks, can be achieved by radio-over-fiber signal generation. As a result, the transmission performance of spectrally efficient radio-over-fiber signaling, including orthogonal frequency division multiplexing and orthogonal wavelength division multiplexing, is broadly and deeply investigated. On the other hand, radio-over-fiber is also used for the frequency synchronization that can resolve the performance limitation of wireless interconnect systems. A novel wireless interconnects assisted by radio-over-fiber subsystems is proposed in this dissertation. In conclusion, multiple advantageous facets of radio-over-fiber systems can be found in various levels of end-to-end interconnect systems. The rapid development of radio-over-fiber systems will quickly change the conventional appearance of modern communications.PhDCommittee Chair: Gee-Kung Chang; Committee Member: Bernard Kippelen; Committee Member: Shyh-Chiang Shen; Committee Member: Thomas K. Gaylord; Committee Member: Umakishore Ramachandra

Datacenter Design for Future Cloud Radio Access Network.

Cloud radio access network (C-RAN), an emerging cloud service that combines the traditional radio access network (RAN) with cloud computing technology, has been proposed as a solution to handle the growing energy consumption and cost of the traditional RAN. Through aggregating baseband units (BBUs) in a centralized cloud datacenter, C-RAN reduces energy and cost, and improves wireless throughput and quality of service. However, designing a datacenter for C-RAN has not yet been studied. In this dissertation, I investigate how a datacenter for C-RAN BBUs should be built on commodity servers. I first design WiBench, an open-source benchmark suite containing the key signal processing kernels of many mainstream wireless protocols, and study its characteristics. The characterization study shows that there is abundant data level parallelism (DLP) and thread level parallelism (TLP). Based on this result, I then develop high performance software implementations of C-RAN BBU kernels in C++ and CUDA for both CPUs and GPUs. In addition, I generalize the GPU parallelization techniques of the Turbo decoder to the trellis algorithms, an important family of algorithms that are widely used in data compression and channel coding. Then I evaluate the performance of commodity CPU servers and GPU servers. The study shows that the datacenter with GPU servers can meet the LTE standard throughput with 4× to 16× fewer machines than with CPU servers. A further energy and cost analysis show that GPU servers can save on average 13× more energy and 6× more cost. Thus, I propose the C-RAN datacenter be built using GPUs as a server platform. Next I study resource management techniques to handle the temporal and spatial traffic imbalance in a C-RAN datacenter. I propose a “hill-climbing” power management that combines powering-off GPUs and DVFS to match the temporal C-RAN traffic pattern. Under a practical traffic model, this technique saves 40% of the BBU energy in a GPU-based C-RAN datacenter. For spatial traffic imbalance, I propose three workload distribution techniques to improve load balance and throughput. Among all three techniques, pipelining packets has the most throughput improvement at 10% and 16% for balanced and unbalanced loads, respectively.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/120825/1/qizheng_1.pd

HW/SW Co-Design Framework für Hochgeschwindigkeits-OFDM Signalverarbeitung

Im Rahmen dieser Arbeit wurde ein HW/SW Co-Design Framework zur Erstellung angepasster Multiprozessor System-on-Chips entwickelt, womit sich für moderne OFDM-Systeme neue Kompromisse zwischen Leistungsfähigkeit und Flexibilität erzielen lassen. Anhand unterschiedlicher Experimente zur Hochgeschwindigkeits-OFDM Übertragung wurde die Funktionalität der Systeme nachgewiesen sowie Datenraten im Gb/s-Bereich erzielt, was bisher lediglich unflexiblen, dedizierten Schaltkreisen vorbehalten war

Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies

Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support

Energy-Efficient Digital Signal Processing Hardware Design.

As CMOS technology has developed considerably in the last few decades, many SoCs have been implemented across different application areas due to reduced area and power consumption. Digital signal processing (DSP) algorithms are frequently employed in these systems to achieve more accurate operation or faster computation. However, CMOS technology scaling started to slow down recently and relatively large systems consume too much power to rely only on the scaling effect while system power budget such as battery capacity improves slowly. In addition, there exist increasing needs for miniaturized computing systems including sensor nodes that can accomplish similar operations with significantly smaller power budget. Voltage scaling is one of the most promising power saving techniques due to quadratic switching power reduction effect, making it necessary feature for even high-end processors. However, in order to achieve maximum possible energy efficiency, systems should operate in near or sub-threshold regimes where leakage takes significant portion of power. In this dissertation, a few key energy-aware design approaches are described. Considering prominent leakage and larger PVT variability in low operating voltages, multi-level energy saving techniques to be described are applied to key building blocks in DSP applications: architecture study, algorithm-architecture co-optimization, and robust yet low-power memory design. Finally, described approaches are applied to design examples including a visual navigation accelerator, ultra-low power biomedical SoC and face detection/recognition processor, resulting in 2~100 times power savings than state-of-the-art.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110496/1/djeon_1.pd

Advanced Digital Signal Processing Techniques for High-Speed Optical Links

L'abstract è presente nell'allegato / the abstract is in the attachmen