Emulating Digital Logic using Transputer Networks (Very High Parallelism = Simplicity = Performance)

Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a profound impact on the design rules for the controlling software. In particular, the criteria for judging efficiency of the algorithms will be somewhat different. This paper explores some of these implications through the development of highly parallel and highly distributable algorithms based on occam and transputer networks. The major results reported are a new simplicity for software designs, a corresponding ability to reason (formally and informally) about their properties, the reusability of their components and some real performance figures which demonstrate their practicality. Some guidelines to assist in these designs are also given. As a vehicle for discussion, an interactive simulator is developed for checking the functional and timing characteristics of digital logic circuits of arbitrary complexity

Testing and Modeling Ethernet Switches and Networks for Use in ATLAS High-level Triggers

The ATLAS second level trigger will use a multi-layered LAN network to transfer 5 Gbyte/s detector data from ~1500 buffers to a few hundred processors. A model of the network has been constructed to evaluate its performance. A key component of the network model is a model of an individual switch, reproducing the behavior measured in real devices. A small number of measurable parameters are used to model a variety of commercial Ethernet switches. Using parameters measured on real devices, the impact on the overall network performance is modeled. In the Atlas context, both 100 Mbit and Gigabit Ethernet links are required. A system is described which is capable of characterizing the behavior of commercial switches with the required number of nodes under traffic conditions resembling those to be encountered in the Atlas experiment. Fast Ethernet traffic is provided by a high density, custom built tester based on FPGAs, programmed in Handel-C and VHDL, while the Gigabit Ethernet traffic is generated using Alteon NICs with custom firmware. The system is currently being deployed with 32 100Mbit ports and 16 Gigabit ports, and will be expanded to ~256 nodes of 100 Mbit and ~50 GBE nodes

A constraint-based WCET computation framework

National audienceOTAWA is a tool dedicated to the WCET computation of critical real-time systems. The tool was enhanced in order to take into account modern micro-architecture features, through an ADL-based approach. Architecture constraints are expresses such that they can be solved by well known efficient constraint solvers. In this paper, we present how we could describe some complex architecture features using the Sim-nML language. We are also concerned by the validation and the animation point of views

Architectures for block Toeplitz systems

In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given

A method to generate occam skeletons from formal specifications

We consider the problem of automatically generating parallel programs in the occam language. In particular, we are concerned with the generation of program skeletons, that define just those computations that are common to a number of similar systems leaving empty or 'stub' functions or processes in the code which are to be filled in later in an application-specific manner. Rather than attempt to solve the problem for arbitrary parallel systems, we focus on data-parallel systems composed of iterative processes. In this paper, we propose an implementation strategy for a cellular automaton. Only uniprocessor occam code is considered

A Concurrent Programming Language for Arduino and Educational Robotics

Arduino is currently one of the most popular platforms for educational robotics due to its low cost and large amount of available resources online. The Arduino software library provides an abstraction layer over the hardware details, making it possible for novices to build interesting projects. However, its lack of support for concurrency makes some educational robotics projects difficult. In this paper, we explore different approaches to solve this problem and we propose the implementation of a concurrent programming language supported by a virtual machine running on the Arduino board.XVI Workshop Tecnología Informática Aplicada en Educación (WTIAE).Red de Universidades con Carreras en Informática (RedUNCI

A Concurrent Programming Language for Arduino and Educational Robotics

Arduino is currently one of the most popular platforms for educational robotics due to its low cost and large amount of available resources online. The Arduino software library provides an abstraction layer over the hardware details, making it possible for novices to build interesting projects. However, its lack of support for concurrency makes some educational robotics projects difficult. In this paper, we explore different approaches to solve this problem and we propose the implementation of a concurrent programming language supported by a virtual machine running on the Arduino board.XVI Workshop Tecnología Informática Aplicada en Educación (WTIAE).Red de Universidades con Carreras en Informática (RedUNCI