457 research outputs found
Speed Binning Aware Design Methodology to Improve Profit under Parameter Variations
Abstract-Designin
vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells
In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorizationPreprin
Via-configurable transistors array: a regular design technique to improve ICs yield
Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Our objective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-Ripple Adders from 4 bits to 64 bits.Peer ReviewedPostprint (published version
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors
In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations.Preprin
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Improving timing verification and delay testing methodologies for IC designs
textThe task of ensuring the correct temporal behavior of IC designs,
both before and after fabrication, is extremely important. It is becoming
even more imperative as the demand for performance increases and process
technology advances into the deep sub-micron region.
This dissertation tackles the key issues in the timing verification
and delay testing methodologies. An efficient methodology is presented to
identify false timing paths in the timing verification methodology which utilizes
ATPG technique and timing information from an ordered list of timing
paths according to the delay information. This dissertation also presents a
speed binning methodology which utilizes structural delay tests successfully
instead of functional tests. In addition, it establishes a methodology which
quantifies the correlation between the timing verification prediction and
actual silicon measurement of timing paths. This quantification methodology
lays the foundation for further research to study the impact of deep
submicron effects on design performanceElectrical and Computer Engineerin
CAD Techniques for Robust FPGA Design Under Variability
The imperfections in the semiconductor fabrication process and uncertainty in operating environment of VLSI circuits have emerged as critical challenges for the semiconductor industry. These are generally termed as process and environment variations, which lead to uncertainty in
performance and unreliable operation of the circuits. These problems have been
further aggravated in scaled nanometer technologies due to increased process
variations and reduced operating voltage.
Several techniques have been proposed recently for designing digital VLSI circuits
under variability. However, most of them have targeted ASICs and custom designs.
The flexibility of reconfiguration and unknown end application in FPGAs
make design under variability different for FPGAs compared to
ASICs and custom designs, and the techniques proposed for ASICs and custom designs cannot be directly applied
to FPGAs. An important design consideration is to minimize the modifications in architecture and circuit
to reduce the cost of changing the existing FPGA architecture and circuit.
The focus of this work can be divided into three principal categories, which are, improving
timing yield under process variations, improving power yield under process variations and improving the voltage profile
in the FPGA power grid.
The work on timing yield improvement proposes routing architecture enhancements along with CAD techniques to
improve the timing yield of FPGA designs. The work on power yield improvement for FPGAs selects a low power dual-Vdd FPGA design
as the baseline FPGA architecture for developing power yield enhancement techniques. It proposes CAD techniques to improve the
power yield of FPGAs. A mathematical programming technique is proposed to determine the parameters
of the buffers in the interconnect such as the sizes of the transistors and threshold voltage of the transistors, all
within constraints, such that the leakage variability is minimized under delay constraints.
Two CAD techniques are investigated and proposed to improve the supply voltage profile of
the power grids in FPGAs. The first technique is a place and route technique and the second technique
is a logic clustering technique to reduce IR-drops and spatial variation of supply voltage in the power grid
A Dynamic Back End of the Line Customization Technique for Yield Improvement
Abstract
A Dynamic Back End of the Line Customization Technique for
Yield Improvement
Ardavan Aryanpour, M. Sc
July 2010
As CMOS technology evolves and transistors get smaller, although chip
manufacturers benefit significantly from being able to fit more transistors in a
smaller area and also producing chips with lower power dissipation, they have
to confront newer problems that are directly related to the size of transistors
and the thickness of the deposited layers on a wafer.
Smaller transistors are faster and dissipate less power, but the smaller the
technology becomes, the harder the fabrication process is to control. Thin
silicon, metal and oxide layers must be accurately deposited because any
variation in the thickness will cause unexpected behavior in the device.
These variations affect many parameters in CMOS. Any slight change in
temperature, doping density, deposition timing, etc., can cause a significant
change of characteristics of a CMOS device and the variation caused by these
changes is called Process Variation (PV).
In this thesis, two circuits are taken into study in order to understand how
process variation impacts the electrical specifications of a circuit example.
The first example is a tapered buffer chain and the second example is a senseamplifier
flip flop. The idea is to propose a technique to decrease the loss
percentage (Increase the yield). Basically for one specific design a few variant
circuit layouts with different power-speed specifications are implemented and
based on the results of the mid fabrication measurements on the test circuits
that are deposited throughout the wafer, one of them is chosen with the means
of choosing a proper masking sequence. The electrical characteristics of the
i
Reliability in the face of variability in nanometer embedded memories
In this thesis, we have investigated the impact of parametric variations on the behaviour of one performance-critical processor structure - embedded memories. As variations manifest as a spread in power and performance, as a first step, we propose a novel modeling methodology that helps evaluate the impact of circuit-level optimizations on architecture-level design choices. Choices made at the design-stage ensure conflicting requirements from higher-levels are decoupled. We then complement such design-time optimizations with a runtime mechanism that takes advantage of adaptive body-biasing to lower power whilst improving performance in the presence of variability. Our proposal uses a novel fully-digital variation tracking hardware using embedded DRAM (eDRAM) cells to monitor run-time changes in cache latency and leakage. A special fine-grain body-bias generator uses the measurements to generate an optimal body-bias that is needed to meet the required yield targets. A novel variation-tolerant and soft-error hardened eDRAM cell is also proposed as an alternate candidate for replacing existing SRAM-based designs in latency critical memory structures. In the ultra low-power domain where reliable operation is limited by the minimum voltage of operation (Vddmin), we analyse the impact of failures on cache functional margin and functional yield. Towards this end, we have developed a fully automated tool (INFORMER) capable of estimating memory-wide metrics such as power, performance and yield accurately and rapidly. Using the developed tool, we then evaluate the #effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Having a holistic perspective of memory-wide metrics helps us arrive at design-choices optimized simultaneously for multiple metrics needed for maintaining lifetime requirements
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