Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

Visualization designs for constraint logic programming

We address the design and implementation of visual paradigms for observing the execution of constraint logic programs, aiming at debugging, tuning and optimization, and teaching. We focus on the display of data in CLP executions, where representation for constrained variables and for the constrains themselves are seeked. Two tools, VIFID and TRIFID, exemplifying the devised depictions, have been implemented, and are used to showcase the usefulness of the visualizations developed

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

A hard-sphere model on generalized Bethe lattices: Statics

We analyze the phase diagram of a model of hard spheres of chemical radius one, which is defined over a generalized Bethe lattice containing short loops. We find a liquid, two different crystalline, a glassy and an unusual crystalline glassy phase. Special attention is also paid to the close-packing limit in the glassy phase. All analytical results are cross-checked by numerical Monte-Carlo simulations.Comment: 24 pages, revised versio

Efficient Groundness Analysis in Prolog

Boolean functions can be used to express the groundness of, and trace grounding dependencies between, program variables in (constraint) logic programs. In this paper, a variety of issues pertaining to the efficient Prolog implementation of groundness analysis are investigated, focusing on the domain of definite Boolean functions, Def. The systematic design of the representation of an abstract domain is discussed in relation to its impact on the algorithmic complexity of the domain operations; the most frequently called operations should be the most lightweight. This methodology is applied to Def, resulting in a new representation, together with new algorithms for its domain operations utilising previously unexploited properties of Def -- for instance, quadratic-time entailment checking. The iteration strategy driving the analysis is also discussed and a simple, but very effective, optimisation of induced magic is described. The analysis can be implemented straightforwardly in Prolog and the use of a non-ground representation results in an efficient, scalable tool which does not require widening to be invoked, even on the largest benchmarks. An extensive experimental evaluation is givenComment: 31 pages To appear in Theory and Practice of Logic Programmin

A Review of the Erosion of Thermal Barrier Coatings.

The application of thermal barrier coatings (TBCs) to components with internal cooling in the hot gas stream of gas turbine engines has facilitated a steep increase in the turbine entry temperature and the associated increase in performance and efficiency of gas turbine engines. However, TBCs are susceptible to various life limiting issues associated with their operating environment including erosion, corrosion, oxidation, sintering and foreign object damage (FOD). This is a review paper that examines various degradation and erosion mechanisms of TBCs, especially those produced by electron beam physical vapour deposition (EB-PVD). The results from a number of laboratory tests under various impact conditions are discussed before the different erosion and FOD mechanisms are reviewed. The transitions between the various erosion mechanisms are discussed in terms of the D/d ratio (contact area diameter/column diameter), a relatively new concept that relates the impact size to the erosion mechanism. The effects of ageing, dopant additions and calciumâ  magnesiumâ  aluminaâ  silicates on the life of TBCs are examined. It is shown that while ageing increases the erosion rate of EB-PVD TBCs, ageing of plasma sprayed TBCs in fact lowers the erosion rate. Finally modelling of EB-PVD TBCs is briefly intr

The effect of contact torques on porosity of cohesive powders

The porosity of uniaxially compacted cohesive powders depends on the applied stress (including gravity). The case, where these stresses are weak, is considered. The compaction results in a porosity which is a function of sliding, rolling and torsion friction. By contact dynamics simulations it is shown that the influences of contact torques (static rolling and torsion friction) on the porosity are significant and approximately additive. The relevance for nano-powder pressure sintering is discussed.Comment: 5 pages, 5 figure