Analysis of the Effects of Impurities in Silicon

A solar cell fabrication and analysis program was conducted to determine the effects on the resultant solar cell efficiency of impurities intentionally incorporated into silicon. The program employed flight quality technologies and quality assurance to assure that variations in cell performance were due to the impurities incorporated in the silicon. The initial verification runs have resulted in an average AM0 cell efficiency of 12.8% at 25 C

Process techniques study of integrated circuits Final scientific report

Surface impurity and structural defect analysis on thermally grown silicon oxide integrated circui

OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above

Monatomic phase change memory

Phase change memory has been developed into a mature technology capable of storing information in a fast and non-volatile way, with potential for neuromorphic computing applications. However, its future impact in electronics depends crucially on how the materials at the core of this technology adapt to the requirements arising from continued scaling towards higher device densities. A common strategy to finetune the properties of phase change memory materials, reaching reasonable thermal stability in optical data storage, relies on mixing precise amounts of different dopants, resulting often in quaternary or even more complicated compounds. Here we show how the simplest material imaginable, a single element (in this case, antimony), can become a valid alternative when confined in extremely small volumes. This compositional simplification eliminates problems related to unwanted deviations from the optimized stoichiometry in the switching volume, which become increasingly pressing when devices are aggressively miniaturized. Removing compositional optimization issues may allow one to capitalize on nanosize effects in information storage

Development and testing of a micromachined probe card.

This thesis is concerned with the design, fabrication and testing of micro scale probes. The probes were designed to act as temporary electrical connections to allow wafer level testing of integrated circuits. The work initially focused on the creation of free standing nickel cantilevers, angled up from the substrate with probe tips at the free end. These were fabricated using a novel method, combining pseudo grey scale lithography and thick photoresist sacrificial layers. Detailed analysis of the fabrication method, in particular the resist processing and lithography was undertaken and the limitations of the method explored.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Silicon Solar Cell Process Development, Fabrication and Analysis, Phase 1

Solar cells from RTR ribbons, EFG (RF and RH) ribbons, dendritic webs, Silso wafers, cast silicon by HEM, silicon on ceramic, and continuous Czochralski ingots were fabricated using a standard process typical of those used currently in the silicon solar cell industry. Back surface field (BSF) processing and other process modifications were included to give preliminary indications of possible improved performance. The parameters measured included open circuit voltage, short circuit current, curve fill factor, and conversion efficiency (all taken under AM0 illumination). Also measured for typical cells were spectral response, dark I-V characteristics, minority carrier diffusion length, and photoresponse by fine light spot scanning. the results were compared to the properties of cells made from conventional single crystalline Czochralski silicon with an emphasis on statistical evaluation. Limited efforts were made to identify growth defects which will influence solar cell performance

Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization

This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55°C to 125°C, 15°C/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region

Horn-Coupled, Commercially-Fabricated Aluminum Lumped-Element Kinetic Inductance Detectors for Millimeter Wavelengths

We discuss the design, fabrication, and testing of prototype horn-coupled, lumped-element kinetic inductance detectors (LEKIDs) designed for cosmic microwave background (CMB) studies. The LEKIDs are made from a thin aluminum film deposited on a silicon wafer and patterned using standard photolithographic techniques at STAR Cryoelectronics, a commercial device foundry. We fabricated twenty-element arrays, optimized for a spectral band centered on 150 GHz, to test the sensitivity and yield of the devices as well as the multiplexing scheme. We characterized the detectors in two configurations. First, the detectors were tested in a dark environment with the horn apertures covered, and second, the horn apertures were pointed towards a beam-filling cryogenic blackbody load. These tests show that the multiplexing scheme is robust and scalable, the yield across multiple LEKID arrays is 91%, and the noise-equivalent temperatures (NET) for a 4 K optical load are in the range 26\thinspace\pm6 \thinspace \mu \mbox{K} \sqrt{\mbox{s}}

Towards flexible asymmetric MSM structures using Si microwires through contact printing

This paper presents development of flexible metal-semiconductor-metal devices using silicon (Si) microwires. Monocrystalline Si in the shape of microwires are used which are developed through standard photolithography and etching. These microwires are assembled on secondary flexible substrates through a dry transfer printing by using a polydimethylsiloxane stamp. The conductive patterns on Si microwires are printed using a colloidal silver nanoparticles based solution and an organic conductor i.e. poly (3,4-ethylene dioxthiophene) doped with poly (styrene sulfonate). A custom developed spray coating technique is used for conductive patterns on Si microwires. A comparative study of the current–voltage (I–V) responses is carried out in flat and bent orientations as well as the response to the light illumination of the wires is explored. Current variations as high as 17.1 μA are recorded going from flat to bend conditions, while the highest I on/I off ratio i.e. 43.8 is achieved with light illuminations. The abrupt changes in the current response due to light-on/off conditions validates these devices for fast flexible photodetector switches. These devices are also evaluated based on transfer procedure i.e. flip-over and stamp-assisted transfer printing for manipulating Si microwires and their subsequent post-processing. These new developments were made to study the most feasible approach for transfer printing of Si microwires and to harvest their capabilities such as photodetection and several other applications in the shape of metal-semiconductor-metal structures

Space station power semiconductor package

A package of high-power switching semiconductors for the space station have been designed and fabricated. The package includes a high-voltage (600 volts) high current (50 amps) NPN Fast Switching Power Transistor and a high-voltage (1200 volts), high-current (50 amps) Fast Recovery Diode. The package features an isolated collector for the transistors and an isolated anode for the diode. Beryllia is used as the isolation material resulting in a thermal resistance for both devices of .2 degrees per watt. Additional features include a hermetical seal for long life -- greater than 10 years in a space environment. Also, the package design resulted in a low electrical energy loss with the reduction of eddy currents, stray inductances, circuit inductance, and capacitance. The required package design and device parameters have been achieved. Test results for the transistor and diode utilizing the space station package is given