Imperfection-Aware Design of CNFET Digital VLSI Circuits

Carbon nanotube field-effect transistor (CNFET) is one of the promising candidates as extensions to silicon CMOS devices. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device characteristics, gate and system levels delays. The analytical models, which were validated by comparison to real experimental/simulation data, enables us to examine the space of CNFET combinational, sequential and memory cells circuits to minimize delay variations. Using these model, we drive CNFET processing and circuit design guidelines to manage/overcome CNT density variation. 2) Analytical models that are developed to analyze the effects of metallic CNTs on device characteristics, gate and system levels delay and power consumption. Using our presented analytical models, which are again validated by comparison with simulation data, it is shown that the static power dissipation is a more critical issue than the delay and the dynamic power of CNFET circuits in the presence of m-CNTs. 3) CNT density variation and metallic CNTs can result in functional failure of CNFET circuits. The complete and compact model for CNFET probability of failure that consider CNT density variation and m-CNTs is presented. This analytical model is applied to analyze the logical functional failures. The presented model is extended to predict opportunities and limitations of CNFET technology at todays Gigascale integration and beyond.\u2

New Logic Synthesis As Nanotechnology Enabler (invited paper)

Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high- performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance

Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with Moore¿s Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

Robust Circuit & Architecture Design in the Nanoscale Regime

Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates. This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield. In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of CNFET based gates and in the worst case open circuit gates. A Monte Carlo simulation engine is developed to estimate the impact of the removal of tubes on the performance and power of CNFET based logic gates. For a quick estimation of functional yield of logic gates, accurate analytical models are developed to estimate the functional yield of logic gates when a fraction of the tubes are removed. An efficient tube level redundancy (TLR) is proposed, resulting in a high functional yield of carbon nanotube based circuits with minimal overheads in terms of area and power when large fraction of tubes are removed. Furthermore, for applications where parallelism can be utilized we propose to increase the functional yield of the CNFET based circuits by increasing the logic depth of gates

Intégration 3D des transistors à nanofils de silicium-germanium sur puces CMOS

La microélectronique est partout dans notre vie : les téléphones intelligents, les jeux vidéo ainsi que d’autres appareils électroniques que nous tenons dans le creux de la main. Les besoins en performances et en gestion d’énergie se font de plus en plus ressentir. Le recours à la miniaturisation des transistors a permis l’amélioration des performances de ces composants au cours des années. Cette tendance a suivi la célèbre loi de « Moore » qui a prévu que la densité des transistors doublerait sur une même puce tous les 2 ans. Aujourd’hui cette loi de « Moore » doit faire face à des limites physiques et technologiques et c’est ainsi que le besoin d’intégrer de nouvelles fonctionnalités commence à apparaitre. L’empilement vertical des composants est une solution alternative étudiée pour faire face aux difficultés inhérentes à l’intégration planaire. Aujourd'hui, les circuits intégrés en 3D ont montré des gains de puissance significatifs pour différents types d’applications (mémoire...). Cette technologie repose sur des interconnexions verticales entre les différents niveaux connus sous le nom de « Through Silicon Vias » (TSVs). Différentes stratégies sont adoptées pour ce type d’empilement dans lesquelles l'intégration 3D monolithique est une approche qui offre la possibilité d’élaborer les différentes étapes technologiques directement sur une même puce. Une difficulté majeure de cette technologie réside dans le processus de fabrication des circuits dans les couches supérieures : Les étapes de la fabrication dans le « backend- of-line (BEOL) » ne doivent en aucun cas perturber le fonctionnement des transistors du « front-end-of-line (FEOL) ». C’est pour cette raison, le budget thermique doit être inférieure à 500 °C afin de préserver les performances des dispositifs dans la partie frontale de la ligne (FEOL). Récemment, des nanofils semi-conducteurs préparés dans un bâti de CVD « chemical vapor deposition », ont suscité un nouvel intérêt pour la fabrication de nanodispositifs. Cette technique ascendante fournit des nanofils monocristallins avec le respect du budget thermique requis pour les processus d'intégration en 3D. Elle permet la synthèse des nanofils à des dimensions réduites avec un large choix de matériaux et de compositions. Les travaux de cette thèse portent sur l’idée de démontrer que la croissance des nanofils entre deux électrodes prédéfinies et plus particulièrement la croissance horizontale à l’intérieur des tranchées d’oxyde peut être utilisée dans l’optique d’une intégration 3D. Cela permettrait donc à terme de pouvoir directement fabriquer les couches actives semi-conductrices d’un transistor MOS dans les niveaux supérieurs d’une puce CMOS tout en respectant le budget thermique et sans avoir recours à des étapes de collage de puces. Au cours de ce projet de recherche, nous nous sommes intéressés en premier lieu au développement et à l’optimisation du procédé qu’on appelle « nanodamascène » mis en place pour guider des nanofils SiGe dans des tranchées d’oxyde directement sur un substrat SiO2/Si. À part de cette technique d’intégration, nous avons aussi utilisé la technique de diélectrophorèse pour localiser des nanofils dispersés dans une solution liquide de manière horizontale entre des électrodes prédéfinies. Les résultats de la localisation ont permis de fabriquer des transistors à canaux nanofils sur l’oxyde et à terme de montrer la possibilité d’établir un transistor dans le BEOL d’une puce CMOS