Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit

Development of a Waveform Sampling ASIC with Femtosecond Timing for a Low Occupancy Vertex Detector.

Ph.D. Thesis. University of Hawaiʻi at Mānoa 2018

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color filters are investigated as alternative to conventional color filters and their feasibility for spectroscopy demonstrated through reconstruction of 6 sample spectra by using a set of 20 color filters. The error in reconstructed sample spectra is less than 0.137 root mean squared error across all samples. Part II: A novel 12-bit pipelined successive approximation analog to digital converter is investigated for high speed data conversion. The design was implemented in TSMC 65nm process to demonstrate the feasibility of the architecture. Furthermore, a high dynamic range audio delta sigma modulator using pseudo-pseudo differential topology was investigated and feasibility simulated using TSMC 65nm process. In addition, various novel systems and circuit techniques including efficient calibration of feedback digital to analog converters, new boosted switch and push-pull source follower circuits were investigated to improve upon existing circuit topologies

Design techniques and implementations of high-speed analog communication circuits: two analog-to-digital converters and a 3.125Gb/s receiver

Low-cost and high performance analog building blocks are essentials to the realization of today\u27s high-speed networking and communications systems. Two such building blocks are analog-to-digital converters (ADCs) and multi-gigabit per second transceivers. This thesis addresses two different ADC architectures and a 3.125Gb/s receiver Architecture;The first ADC architecture is a 10-bit, 100MS/s pipeline ADC. Techniques that enhance the gain-bandwidth of the operational amplifier, a key building block in analog-to-digital converters, as well as to increase its do gain are presented. Layout techniques to reduce the effect of parasitics on the performance of the ADC are also discussed. Since any ADC will have inherent errors in it, two calibration techniques that reduce the effect of these errors on the performance of the ADC are also presented.;For the second ADC, a new architecture is proposed that is capable of achieving higher performance than many current ADC architectures. The new architecture is based on a voltage controlled oscillator and a frequency detector. One reason for the high performance of the new ADC is the novel architecture of the frequency detector. This thesis includes detailed analysis as well as examples to illustrate the operation of the frequency detector.;Designing high-speed CMOS transceivers is a challenging process, especially, when using digital CMOS process that exhibits poor analog performance. Circuit implementation and design techniques that are used to design and enhance the performance of the receiver block of a 3.125Gb/s transceiver in a 0.18u digital CMOS process are presented and fully explained in this thesis. Silicon results have shown that these techniques have resulted in outstanding and very robust receiver performance under different operating conditions

Design of high speed folding and interpolating analog-to-digital converter

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate

Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs

During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however most of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu- tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC element mismatch constraints are critical but not insurmountable at 10 bits of resolution or less in sub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs (11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraint still dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors. The focus of this work is to extend the scaling benefits of the SAR architecture to medium and higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138630/1/ncolins_1.pd

High-speed flash adc design

Master'sMASTER OF ENGINEERIN

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW