Adiabatic Circuits for Power-Constrained Cryptographic Computations

This thesis tackles the need for ultra-low power operation in power-constrained cryptographic computations. An example of such an application could be smartcards. One of the techniques which has proven to have the potential of rendering ultra-low power operation is ‘Adiabatic Logic Technique’. However, the adiabatic circuits has associated challenges due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors is considered for the power-clock generation and several design rules and trade-offs between the circuit complexity and energy efficiency of the PCG using n-step charging circuits have been proposed. Since pipelining is inherent in adiabatic logic design, careful selection of architecture is essential, as otherwise overhead in terms of area and energy due to synchronization buffers is induced specifically, in the case of adiabatic designs using 4-phase power-clocking scheme. Several architectures for the Montgomery multiplier using adiabatic logic technique are implemented and compared. An architecture which constitutes an appropriate trade-off between energy efficiency and throughput is proposed along with its methodology. Also, a strategy to reduce the overhead due to synchronization buffers is proposed. A modification in the Montgomery multiplication algorithm is proposed. Furthermore, a problem due to the application of power-clock gating in cascade stages of adiabatic logic is identified. The problem degrades the energy savings that would otherwise be obtained by the application of power-clock gating. A solution to this problem is proposed. Cryptographic implementations also present an obvious target for Power Analysis Attacks (PAA). There are several existing secure adiabatic logic designs which are proposed as a countermeasure against PAA. Shortcomings of the existing logic designs are identified, and two novel secure adiabatic logic designs are proposed as the countermeasures against PAA and improvement over the existing logic designs

Research on low power technology by AC power supply circuits

制度:新 ; 報告番号:甲3692号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6060Waseda Universit

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs

Energy efficiency of 2- Step power-clocks for adiabatic logic

The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parameters such as tank-capacitance to load capacitance ratio, ramping time, transistors sizing and power supply voltage scaling on energy recovery achievable in the 2-step charging circuit. We show that energy recovery achievable in the 2-step charging circuit depends on the tank-capacitor and load capacitor size concluding that tank-capacitance (CT) versus load capacitance (CL) is the significant parameter. We also show that the energy performance depends on the ramping time and improves for higher ramping times (lower frequencies). Energy recovery also improves if the transistors sizes in the step charging circuit are sized at their minimum dimensions. Lastly, we show that energy recovery decreases as the power supply voltage is scaled down. Specifically, the decrease in the energy recovery with decreasing power supply is significant for lower ramping times (higher frequencies). We propose that a Ct/Cl ratio of 10, keeping the width of the transistors in the step charging circuit minimum, can be chosen as a convenient `rule-of-thumb' in practical designs

Power Optimization in Johnson Counter through Clock Gating with Static Energy Recovery Logic

In the latest designs of VLSI, power dissipation is the main charge to take care. The dependency on micro electronics is rising as the size of chip is being compact & also the systems with minimal power are being prioritized. The computer systems are comprised of sequential circuitries & this is the reason that designs having minimal power absorption gave gained priority. In this document, we have suggested a schema on minimal power of Johnson Counter by employing a clock gating system & pass transistors in D flip flop. By making few judgements on power in SPICE, it is presumed that he suggested system design leads to minimal power decadence & has simple interlinking in contrast to the complicated traditional designs. In this document we put the outcomes of power in contrast in four methods that are TG ADCL i.e. Adiabatic Dynamic CMOS Logic, TG QSERL i.e. Quai static energy recovery logic, TG normal & TG split level pulse. Power has risen too high in TG ADCL, TG QSERL & TG normal

Low Power Dissipation in Johnson Counter using DFAL Technique

This paper presents a new method for minimizing power dissipation in 4-bit Johnson counter in which Diode-Free adiabatic Logic(DFAL) is used.Power dissipation of the diodes is eliminated by removing diodes from charging and discharging path.Performance of the proposed logic is analyzed and compared with that of CMOS based circuits. All the simulation are carried out in VIRTUOSO spectre simulator of CADENCE 90nm technology .The paper provides low power dissipation using DFAL logic,which has shown better improvement than conventional CMOS design

Implementation of Low Power Multiplexer usign Adiabatic Logic

Adiabatic logic is a low power logic based on charge recovery principle. In this paper, an adiabatic logic based 2x1 multiplexer and 4x1 multiplexer are designed on the basis of Two-Phase Adiabatic Static Clocked Logic (2PASCL) technique. The power dissipation of proposed technique is compared with conventional CMOS technique according to the various values of input signal switching frequencies, number of active devices and total nodes. The simulation is performed on S-edit of TANNER tools with BSIM4 at 90nm technology

Low Power Design Of Asynchronous Fine-Grain Power-Gated Logic

In technology improvement power dissipation has one of the major factor well known short circuit dissipations, leakage dissipations and dynamic switching dissipations are major power dissipation sources of CMOS Chips. For reducing power dissipation in CMOS logic blocks various techniques were there among these techniques most effective new technique implemented with low power dissipation. That is “low power design of Asynchronous fine-grain power gated logic”(LPAFPL). Low power AFPL is a new logic family. It consist of ECRL (efficient charge recovery logic gate), Pipeline system, C-element and Partial Charge Reuse mechanism (PCR). Each pipeline stage is comprised efficient charge recovery logic gate gains power and it is became active when useful computations are there and does not requires power at idle stage. Thus gives negligible leakage power dissipation. PCR is the output node of the ECRL logic, To evaluate the CMOS logic circuit level. Then it automatically reduced the power dissipation in complete evaluation of CMOS circuits

Enhancing Energy Efficiency in VLSI Circuits: Strategies for Dynamic Power Dissipation Reduction

Dynamic power dissipation has historically been a major concern in VLSI circuits and systems, primarily resulting from changes in the output of logic gates. To address this issue, various techniques have been developed to reduce dynamic power consumption by targeting key parameters in the power consumption formula, including capacitance (C), supply voltage (V), clock frequency (f), and switching activity (?). This paper explores strategies such as clock gating, dynamic voltage and frequency scaling (DVFS), and power leakage minimization to enhance energy efficiency in VLSI circuits. Clock gating involves disabling the clock signal to components or the entire system when they are not in use, significantly reducing unnecessary switching activity and saving power. DVFS is a method for conserving energy in battery-powered devices by adjusting voltage and clock frequency based on workload requirements. Power leakage minimization strategies, such as threshold voltage adjustment and power gating, are crucial to reduce leakage currents and enhance energy efficiency in modern semiconductor devices