79,373 research outputs found
A high speed Tri-Vision system for automotive applications
Purpose: Cameras are excellent ways of non-invasively monitoring the interior and exterior of vehicles. In particular, high speed stereovision and multivision systems are important for transport applications such as driver eye tracking or collision avoidance. This paper addresses the synchronisation problem which arises when multivision camera systems are used to capture the high speed motion common in such applications.
Methods: An experimental, high-speed tri-vision camera system intended for real-time driver eye-blink and saccade measurement was designed, developed, implemented and tested using prototype, ultra-high dynamic range, automotive-grade image sensors specifically developed by E2V (formerly Atmel) Grenoble SA as part of the European FP6 project – sensation (advanced sensor development for attention stress, vigilance and sleep/wakefulness monitoring).
Results : The developed system can sustain frame rates of 59.8 Hz at the full stereovision resolution of 1280 × 480 but this can reach 750 Hz when a 10 k pixel Region of Interest (ROI) is used, with a maximum global shutter speed of 1/48000 s and a shutter efficiency of 99.7%. The data can be reliably transmitted uncompressed over standard copper Camera-Link® cables over 5 metres. The synchronisation error between the left and right stereo images is less than 100 ps and this has been verified both electrically and optically. Synchronisation is automatically established at boot-up and maintained during resolution changes. A third camera in the set can be configured independently. The dynamic range of the 10bit sensors exceeds 123 dB with a spectral sensitivity extending well into the infra-red range.
Conclusion: The system was subjected to a comprehensive testing protocol, which confirms that the salient requirements for the driver monitoring application are adequately met and in some respects, exceeded. The synchronisation technique presented may also benefit several other automotive stereovision applications including near and far-field obstacle detection and collision avoidance, road condition monitoring and others.Partially funded by the EU FP6 through the IST-507231 SENSATION project.peer-reviewe
A survey of scan-capture power reduction techniques
With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing
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Assessment of mechanical properties and microstructure characterizing techniques in their ability to quantify amount of cold work in 316l alloy
Stress corrosion cracking (SCC) behavior is a matter of concern for structural materials, namely, stainless steels and nickel alloys, in nuclear power plants. High levels of cold work (CW) have shown to both reduce crack initiation times and increase crack growth rates. Cold working has numerous effects on a material, including changes in microstructure, mechanical properties, and residual stress state, yet it is typically reported as a simple percent change in geometry. There is need to develop a strategy for quantitative assessment of cold-work level in order to better understand stress corrosion cracking test data. Five assessment techniques, commonly performed alongside stress corrosion cracking testing (optical microscopy (OM), electron backscatter diffraction (EBSD), X-ray diffraction (XRD), tensile testing, and hardness testing) are evaluated with respect to their ability to quantify the level of CW in a component. The test material is stainless steel 316L that has been cold-rolled to three conditions: 0%, 20%, and 30% CW. Measurement results for each assessment method include correlation with CW condition and repeatability data. Measured values showed significant spatial variation, illustrating that CW level is not uniform throughout a component. Mechanical properties (tensile testing, hardness) were found to correlate most linearly with the amount of imparted CW
Improving elevation resolution in phased-array inspections for NDT
The Phased Array Ultrasonic Technique (PAUT) offers great advantages over the conventional ultrasound technique (UT), particularly because of beam focusing, beam steering and electronic scanning capabilities. However, the 2D images obtained have usually low resolution in the direction perpendicular to the array elements, which limits the inspection quality of large components by mechanical scanning. This paper describes a novel approach to improve image quality in these situations, by combining three ultrasonic techniques: Phased Array with dynamic depth focusing in reception, Synthetic Aperture Focusing Technique (SAFT) and Phase Coherence Imaging (PCI). To be applied with conventional NDT arrays (1D and non-focused in elevation) a special mask to produce a wide beam in the movement direction was designed and analysed by simulation and experimentally. Then, the imaging algorithm is presented and validated by the inspection of test samples. The obtained images quality is comparable to that obtained with an equivalent matrix array, but using conventional NDT arrays and equipments, and implemented in real time.Fil: Brizuela, Jose David. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Camacho, J.. Consejo Superior de Investigaciones Científicas; EspañaFil: Cosarinsky, Guillermo Gerardo. Comisión Nacional de Energía Atómica; ArgentinaFil: Iriarte, Juan Manuel. Comisión Nacional de Energía Atómica; ArgentinaFil: Cruza, Jorge F.. Consejo Superior de Investigaciones Científicas; Españ
Simultaneous multiplane imaging with reverberation multiphoton microscopy
Multiphoton microscopy (MPM) has gained enormous popularity over the years for its capacity to provide high resolution images from deep within scattering samples1. However, MPM is generally based on single-point laser-focus scanning, which is intrinsically slow. While imaging speeds as fast as video rate have become routine for 2D planar imaging, such speeds have so far been unattainable for 3D volumetric imaging without severely compromising microscope performance. We demonstrate here 3D volumetric (multiplane) imaging at the same speed as 2D planar (single plane) imaging, with minimal compromise in performance. Specifically, multiple planes are acquired by near-instantaneous axial scanning while maintaining 3D micron-scale resolution. Our technique, called reverberation MPM, is well adapted for large-scale imaging in scattering media with low repetition-rate lasers, and can be implemented with conventional MPM as a simple add-on.Accepted manuscrip
Exposing errors related to weak memory in GPU applications
© 2016 ACM.We present the systematic design of a testing environment that uses stressing and fuzzing to reveal errors in GPU applications that arise due to weak memory effects. We evaluate our approach on seven GPUS spanning three NVIDIA architectures, across ten CUDA applications that use fine-grained concurrency. Our results show that applications that rarely or never exhibit errors related to weak memory when executed natively can readily exhibit these errors when executed in our testing environment. Our testing environment also provides a means to help identify the root causes of such errors, and automatically suggests how to insert fences that harden an application against weak memory bugs. To understand the cost of GPU fences, we benchmark applications with fences provided by the hardening strategy as well as a more conservative, sound fencing strategy
REDUCING POWER DURING MANUFACTURING TEST USING DIFFERENT ARCHITECTURES
Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test.
In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We group the control bits together into one or more control chains.
To address the extra pin(s) required to shift data into the control chain(s) and significant post processing in the first architecture, we explored a second architecture. The second architecture stitches the control bits into the chains they control as EECBs (embedded enable capture bits) in between the segments. This allows an ATPG software tool to automatically generate the appropriate EECB values for each pattern to maintain the fault coverage. This also works in the presence of an on-chip decompressor.
The last architecture focuses primarily on the self-test of a device in a 3D stacked IC when an existing FPGA in the stack can be programmed as a tester. We show that the energy expended during test is significantly less than would be required using low power patterns fed by an on-chip decompressor for the same very short scan chains
Algorithms for Power Aware Testing of Nanometer Digital ICs
At-speed testing of deep-submicron digital very large scale integrated (VLSI) circuits
has become mandatory to catch small delay defects. Now, due to continuous shrinking
of complementary metal oxide semiconductor (CMOS) transistor feature size, power
density grows geometrically with technology scaling. Additionally, power dissipation
inside a digital circuit during the testing phase (for test vectors under all fault models
(Potluri, 2015)) is several times higher than its power dissipation during the normal
functional phase of operation. Due to this, the currents that flow in the power grid during
the testing phase, are much higher than what the power grid is designed for (the
functional phase of operation). As a result, during at-speed testing, the supply grid
experiences unacceptable supply IR-drop, ultimately leading to delay failures during
at-speed testing. Since these failures are specific to testing and do not occur during
functional phase of operation of the chip, these failures are usually referred to false
failures, and they reduce the yield of the chip, which is undesirable.
In nanometer regime, process parameter variations has become a major problem.
Due to the variation in signalling delays caused by these variations, it is important to
perform at-speed testing even for stuck faults, to reduce the test escapes (McCluskey
and Tseng, 2000; Vorisek et al., 2004). In this context, the problem of excessive peak
power dissipation causing false failures, that was addressed previously in the context of
at-speed transition fault testing (Saxena et al., 2003; Devanathan et al., 2007a,b,c), also
becomes prominent in the context of at-speed testing of stuck faults (Maxwell et al.,
1996; McCluskey and Tseng, 2000; Vorisek et al., 2004; Prabhu and Abraham, 2012;
Potluri, 2015; Potluri et al., 2015). It is well known that excessive supply IR-drop during
at-speed testing can be kept under control by minimizing switching activity during
testing (Saxena et al., 2003). There is a rich collection of techniques proposed in the past
for reduction of peak switching activity during at-speed testing of transition/delay faults
ii
in both combinational and sequential circuits. As far as at-speed testing of stuck faults
are concerned, while there were some techniques proposed in the past for combinational
circuits (Girard et al., 1998; Dabholkar et al., 1998), there are no techniques concerning
the same for sequential circuits. This thesis addresses this open problem. We
propose algorithms for minimization of peak switching activity during at-speed testing
of stuck faults in sequential digital circuits under the combinational state preservation
scan (CSP-scan) architecture (Potluri, 2015; Potluri et al., 2015). First, we show that,
under this CSP-scan architecture, when the test set is completely specified, the peak
switching activity during testing can be minimized by solving the Bottleneck Traveling
Salesman Problem (BTSP). This mapping of peak test switching activity minimization
problem to BTSP is novel, and proposed for the first time in the literature.
Usually, as circuit size increases, the percentage of don’t cares in the test set increases.
As a result, test vector ordering for any arbitrary filling of don’t care bits
is insufficient for producing effective reduction in switching activity during testing of
large circuits. Since don’t cares dominate the test sets for larger circuits, don’t care
filling plays a crucial role in reducing switching activity during testing. Taking this
into consideration, we propose an algorithm, XStat, which is capable of performing test
vector ordering while preserving don’t care bits in the test vectors, following which, the
don’t cares are filled in an intelligent fashion for minimizing input switching activity,
which effectively minimizes switching activity inside the circuit (Girard et al., 1998).
Through empirical validation on benchmark circuits, we show that XStat minimizes
peak switching activity significantly, during testing.
Although XStat is a very powerful heuristic for minimizing peak input-switchingactivity,
it will not guarantee optimality. To address this issue, we propose an algorithm
that uses Dynamic Programming to calculate the lower bound for a given sequence
of test vectors, and subsequently uses a greedy strategy for filling don’t cares in this
sequence to achieve this lower bound, thereby guaranteeing optimality. This algorithm,
which we refer to as DP-fill in this thesis, provides the globally optimal solution for
minimizing peak input-switching-activity and also is the best known in the literature
for minimizing peak input-switching-activity during testing. The proof of optimality of
DP-fill in minimizing peak input-switching-activity is also provided in this thesis
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