Performance Analysis of CMOS and FinFET based 16-Bit Barrel Shifter

A barrel shifter shifts ‘n’ number of bits in one cycle. Barrel shifter can perform the following functions: shift left logical, shift left arithmetic, rotate left, shift right logical, shift right arithmetic and rotate right. The design of the barrel shifter is purely MUX based will improve its efficiency if Mux consumes less power. The MUX based SLC barrel shifter circuits are designed using Tanner EDA tools. Fin-type field-effect transistors ( FinFETs) are promising substitutes for bulk CMOS in nano - scale circuits. This paper compares the performance of barrel shifter using two different technologies on the basis of power consumption, time delay and power delay product DOI: 10.17762/ijritcc2321-8169.15067

An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling

Voltage Overscaling (VOS) is one of the well-known techniques to increase the energy efficiency of arithmetic units. Also, it can provide significant lifetime improvements, while still meeting the accuracy requirements of inherently error-resilient applications. This paper proposes a generic accuracy-configurable multiplier that employs the VOS at a coarse-grained level (block-level) to reduce the control logic required for applying VOS and its associated overheads, thus enabling a high degree of trade-off between energy consumption and output quality. The proposed configurable Block-Level VOS-based (BL-VOS) multiplier relies on employing VOS in a multiplier composed of smaller blocks, where applying VOS in different blocks results in structures with various output accuracy levels. To evaluate the proposed concept, we implement 8-bit and 16-bit BL-VOS multipliers with various blocks width in a 15-nm FinFET technology. The results show that the proposed multiplier achieves up to 15% lower energy consumption and up to 21% higher output accuracy compared to the state-of-the-art VOS-based multipliers. Also, the effects of Process Variation (PV) and Bias Temperature Instability (BTI) induced delay on the proposed multiplier are investigated. Finally, the effectiveness of the proposed multiplier is studied for two different image processing applications, in terms of quality and energy efficiency.Comment: This paper has been published in IEEE Transactions on Emerging Topics in Computin

TFET-Based power management circuit for RF energy harvesting

This paper proposes a Tunnel FET (TFET)-based power management circuit (PMC) for ultra-low power RF energy harvesting applications. In contrast with conventional thermionic devices, the band-to-band tunneling mechanism of TFETs allows a better switching performance at sub-0.2 V operation. As a result, improved efficiencies in RF-powered circuits are achieved, thanks to increased rectification performance at low power levels and to the reduced energy required for a proper PMC operation. It is shown by simulations that heterojunction TFET devices designed with III-V materials can improve the rectification process at received power levels below -20 dBm (915 MHz) when compared to the application of homojunction III-V TFETs and Si FinFETs. For an available power of -25 dBm, the proposed converter is able to deliver 1.1 µW of average power (with 0.5 V) to the output load with a boost efficiency of 86%.Postprint (author's final draft

Non-volatile hybrid optical phase shifter driven by a ferroelectric transistor

Optical phase shifters are essential elements in photonic integrated circuits (PICs) and function as a direct interface to program the PIC. Non-volatile phase shifters, which can retain information without a power supply, are highly desirable for low-power static operations. Here a non-volatile optical phase shifter is demonstrated by driving a III-V/Si hybrid metal-oxide-semiconductor (MOS) phase shifter with a ferroelectric field-effect transistor (FeFET) operating in the source follower mode. Owing to the various polarization states in the FeFET, multistate non-volatile phase shifts up to 1.25{\pi} are obtained with CMOS-compatible operation voltages and low switching energy up to 3.3 nJ. Furthermore, a crossbar array architecture is proposed to simplify the control of non-volatile phase shifters in large-scale PICs and its feasibility is verified by confirming the selective write-in operation of a targeted FeFET with a negligible disturbance to the others. This work paves the way for realizing large-scale non-volatile programmable PICs for emerging computing applications such as deep learning and quantum computing

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardware accelerators. DNN+NeuroSim is an integrated benchmark framework supporting flexible and hierarchical CIM array design options from a device level, to a circuit level and up to an algorithm level. In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations. First, the parameters of a memory device and CMOS transistor are extracted from the foundry’s process design kit (PDK) and employed in the NeuroSim settings; the peripheral modules and operating dataflow are also configured to be the same as the actual chip implementation. Next, the area, critical path, and energy consumption values from the SPICE simulations at the module level are compared with those from NeuroSim. Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc. We show that the prediction from NeuroSim is precise with chip-level error under 1% after the calibration. Finally, the system-level performance benchmark is conducted with various device technologies and compared with the results before the validation. The general conclusions stay the same after the validation, but the performance degrades slightly due to the post-layout calibration

A Low Power FinFET Charge Pump For Energy Harvesting Applications

Indiana University-Purdue University Indianapolis (IUPUI)With the growing popularity and use of devices under the great umbrella that is the Internet of Things (IoT), the need for devices that are smaller, faster, cheaper and require less power is at an all time high with no intentions of slowing down. This is why many current research efforts are very focused on energy harvesting. Energy harvesting is the process of storing energy from external and ambient sources and delivering a small amount of power to low power IoT devices such as wireless sensors or wearable electronics. A charge pumps is a circuit used to convert a power supply to a higher or lower voltage depending on the specific application. Charge pumps are generally seen in memory design as a verity of power supplies are required for the newer memory technologies. Charge pumps can be also be designed for low voltage operation and can convert a smaller energy harvesting voltage level output to one that may be needed for the IoT device to operate. In this work, an integrated FinFET (Field Effect Transistor) charge pump for low power energy harvesting applications is proposed. The design and analysis of this system was conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 7nm FinFETs from the ASAP7 7nm PDK. The research conducted here takes advantage of some inherent characteristics that are present in FinFET technologies, including low body effects, and faster switching speeds, lower threshold voltage and lower power consumption. The lower threshold voltage of the FinFET is key to get great performance at lower supply voltages. The charge pump in this work is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of $25mV. FinFET technology continues to be a very popular design choice and even though it has been in production since Intel's Ivy-Bridge processor in 2012, it seems that very few efforts have been made to use the advantages of FinFETs for charge pump design. This work shows though simulation that FinFET charge pumps can match the performance of charge pumps implemented in other technologies and should be considered for low power designs such as energy harvesting

Predicting Critical Warps in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis

General purpose graphics processing units (GP-GPU), owing to their enormous thread-level parallelism, can significantly improve the power consumption at the near-threshold (NTC) operating region, while offering close to a super-threshold performance. However, process variation (PV) can drastically reduce the GPU performance at NTC. In this work, choke points—a unique device-level characteristic of PV at NTC—that can exacerbate the warp criticality problem in GPUs have been explored. It is shown that the modern warp schedulers cannot tackle the choke point induced critical warps in an NTC GPU. Additionally, Choke Point Aware Warp Speculator, a circuit-architectural solution is proposed to dynamically predict the critical warps in GPUs, and accelerate them in their respective execution units. The best scheme achieves an average improvement of ∼39% in performance, and ∼31% in energy-efficiency, over one state-of-the-art warp scheduler, across 15 GPGPU applications, while incurring marginal hardware overheads