Scalable Interactive Volume Rendering Using Off-the-shelf Components

This paper describes an application of a second generation implementation of the Sepia architecture (Sepia-2) to interactive volu-metric visualization of large rectilinear scalar fields. By employingpipelined associative blending operators in a sort-last configuration a demonstration system with 8 rendering computers sustains 24 to 28 frames per second while interactively rendering large data volumes (1024x256x256 voxels, and 512x512x512 voxels). We believe interactive performance at these frame rates and data sizes is unprecedented. We also believe these results can be extended to other types of structured and unstructured grids and a variety of GL rendering techniques including surface rendering and shadow map-ping. We show how to extend our single-stage crossbar demonstration system to multi-stage networks in order to support much larger data sizes and higher image resolutions. This requires solving a dynamic mapping problem for a class of blending operators that includes Porter-Duff compositing operators

Hierarchical N-Body problem on graphics processor unit

Galactic simulation is an important cosmological computation, and represents a classical N-body problem suitable for implementation on vector processors. Barnes-Hut algorithm is a hierarchical N-Body method used to simulate such galactic evolution systems. Stream processing architectures expose data locality and concurrency available in multimedia applications. On the other hand, there are numerous compute-intensive scientific or engineering applications that can potentially benefit from such computational and communication models. These applications are traditionally implemented on vector processors. Stream architecture based graphics processor units (GPUs) present a novel computational alternative for efficiently implementing such high-performance applications. Rendering on a stream architecture sustains high performance, while user-programmable modules allow implementing complex algorithms efficiently. GPUs have evolved over the years, from being fixed-function pipelines to user programmable processors. In this thesis, we focus on the implementation of Barnes-Hut algorithm on typical current-generation programmable GPUs. We exploit computation and communication requirements present in Barnes-Hut algorithm to expose their suitability for user-programmable GPUs. Our implementation of the Barnes-Hut algorithm is formulated as a fragment shader targeting the selected GPU. We discuss implementation details, design issues, results, and challenges encountered in programming the fragment shader

Graphics Hardware Implementation of the Parameter-Less Self-Organising Map

This paper presents a highly parallel implementation of a new type of Self-Organising Map (SOM) using graphics hardware. The Parameter-Less SOM smoothly adapts to new data while preserving the mapping formed by previous data. It is therefore in principle highly suited for interactive use, however for large data sets the computational requirements are prohibitive. This paper will present an implementation on commodity graphics hardware which uses two forms of parallelism to signi¯cantly reduce this barrier. The performance is analysed experi- mentally and algorithmically. An advantage to using graphics hardware is that visualisation is essentially free", thus increasing its suitability for interactive exploration of large data sets

FAST: A multi-processed environment for visualization of computational fluid dynamics

Three-dimensional, unsteady, multi-zoned fluid dynamics simulations over full scale aircraft are typical of the problems being investigated at NASA Ames' Numerical Aerodynamic Simulation (NAS) facility on CRAY2 and CRAY-YMP supercomputers. With multiple processor workstations available in the 10-30 Mflop range, we feel that these new developments in scientific computing warrant a new approach to the design and implementation of analysis tools. These larger, more complex problems create a need for new visualization techniques not possible with the existing software or systems available as of this writing. The visualization techniques will change as the supercomputing environment, and hence the scientific methods employed, evolves even further. The Flow Analysis Software Toolkit (FAST), an implementation of a software system for fluid mechanics analysis, is discussed

FAST: A multi-processed environment for visualization of computational fluid

Three dimensional, unsteady, multizoned fluid dynamics simulations over full scale aircraft is typical of problems being computed at NASA-Ames on CRAY2 and CRAY-YMP supercomputers. With multiple processor workstations available in the 10 to 30 Mflop range, it is felt that these new developments in scientific computing warrant a new approach to the design and implementation of analysis tools. These large, more complex problems create a need for new visualization techniques not possible with the existing software or systems available as of this time. These visualization techniques will change as the supercomputing environment, and hence the scientific methods used, evolve ever further. Visualization of computational aerodynamics require flexible, extensible, and adaptable software tools for performing analysis tasks. FAST (Flow Analysis Software Toolkit), an implementation of a software system for fluid mechanics analysis that is based on this approach is discussed

Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline

GPUs are one of the most energy-consuming components for real-time rendering applications, since a large number of fragment shading computations and memory accesses are involved. Main memory bandwidth is especially taxing battery-operated devices such as smartphones. Tile-Based Rendering GPUs divide the screen space into multiple tiles that are independently rendered in on-chip buffers, thus reducing memory bandwidth and energy consumption. We have observed that, in many animated graphics workloads, a large number of screen tiles have the same color across adjacent frames. In this paper, we propose Rendering Elimination (RE), a novel micro-architectural technique that accurately determines if a tile will be identical to the same tile in the preceding frame before rasterization by means of comparing signatures. Since RE identifies redundant tiles early in the graphics pipeline, it completely avoids the computation and memory accesses of the most power consuming stages of the pipeline, which substantially reduces the execution time and the energy consumption of the GPU. For widely used Android applications, we show that RE achieves an average speedup of 1.74x and energy reduction of 43% for the GPU/Memory system, surpassing by far the benefits of Transaction Elimination, a state-of-the-art memory bandwidth reduction technique available in some commercial Tile-Based Rendering GPUs

Freeform User Interfaces for Graphical Computing

報告番号: 甲15222 ; 学位授与年月日: 2000-03-29 ; 学位の種別: 課程博士 ; 学位の種類: 博士(工学) ; 学位記番号: 博工第4717号 ; 研究科・専攻: 工学系研究科情報工学専

Implementing intersection calculations of the ray tracing algorithm with systolic arrays

Ray tracing is one technique that has been used to synthesize realistic images with a computer. Unfortunately, this technique, when implemented in software, is slow and expensive. The trend in computer graphics has been toward the use of special purpose hardware, to speed up the calculations, and, hence, the generation of the synthesized image. This paper describes the design and the operation of a systolic based architecture, tailored to speed up the intersection calculations, that must be performed as a part of the ray tracing algorithm

Gerber File Parsing for Conversion to Bitmap Image–The VINCI7D Case Study

The technological market is increasingly evolving as evidenced by the innovative and streamlined manufacturing processes. Printed Circuit Boards (PCB) are widely employed in the electronics fabrication industry, resorting to the Gerber open standard format to transfer the manufacturing data. The Gerber format describes not only metadata related to the manufacturing process but also the PCB image. To be able to map the electronic circuit pattern to be printed, a parser to convert Gerber files into a bitmap image is required. The current literature as well as available Gerber viewers and libraries showed limitations mainly in the Gerber format support, focusing only on a subset of commands. In this work, the development of a recursive descent approach for parsing Gerber files is described, outlining its interpretation and the renderization of 2D bitmap images. All the defined commands in the specification based on Gerber X2 generation were successfully rendered, unlike the tested commercial parsers used in the experiments. Moreover, the obtained results were comparable to those parsers regarding the commands they can execute as well as the ground-truth, emphasizing the accuracy of the proposed approach. Its top-down and recursive architecture allows easy integration with other software regardless of the platform, highlighting its potential inclusion and integration in the production of electronic circuits.info:eu-repo/semantics/publishedVersio