Characterization of materials and fabrication of active matrix thin film transistor arrays for electrical interfacing of biological materials

Electrical interfacing between semiconductor devices and biological materials has been studied for live cell probing which will make it possible to perform direct electrical sensing of cells. To extend the applicability of extracellular and planar microelectrode arrays, recently vertically aligned nanofibers (VACNFs) have been integrated with micro electrode arrays (MEA) for applications such as cell membrane mimics, gene delivery arrays, neuroelectrochemical interfacing arrays, superhydrophobic switches, and intracellular probes. The main drawback of VACNF-MEA devices are the low density of electrodes and passive addressing approach. In order to increase the number of elements of an MEA and enable both stimulation and recording on the same platform, an actively addressed thin film transistor (TFT) array platform was developed. Active matrix-TFTs are highly functional devices which have been used widely as backplanes in display electronics field over the past few decades.VACNFs were integrated onto the TFT array (TFT-VACNF) as they enhance the electrical sensitivity to the cell relative to standard planar arrays; furthermore, the vertical electrodes provide the potential for intracellular sensing within individual cells. This device platform provides great potential as an advanced microelectrode array for direct cell sensing, probing, and recording with a high electrode density and active addressability. In this study, VACNFs were successfully integrated onto TFT devices to demonstrate a new microelectrode array platform. The materials and processes of the TFT structure were designed to be compatible with the requisite high-temperature (~700°C) and direct current Plasma Enhanced Chemical Vapor Deposition (dc-PECVD) VACNF growth process.To extend the applicability of utilizing these vertical electrodes, this dissertation describes: the characterization and optimization of each layer for the TFT; the fabrication process and issues for active matrix TFT array; the critical device integration issues of VACNFs onto active matrix TFT arrays are elaborated; and the initial and final device characteristics are reported

\u3cem\u3eMaterials Integration and Device Fabrication of Active Matrix Thin Film Transistor Arrays for Intracellular Gene Delivery\u3c/em\u3e

Materials and process integration of a thin film transistor array for intra/extracellular probing are described in this study. A combinatorial rf magnetron sputter deposition technique was employed to investigate the electrical characteristics and micro-structural properties of molybdenum tungsten (MoW) high temperature electrodes as a function of the binary composition. In addition to the composition, the effect of substrate bias and temperature was investigated. The electrical resistivity of MoW samples deposited at room temperature with zero bias followed the typical Nordheim’s rule as a function of composition. The resistivity of samples deposited with substrate bias is uniformly lower and obeyed the rule of mixtures as a function of composition. The metastable β-W phase was not observed in the biased films even when deposited at room temperature. High resolution scanning electron microscopy revealed a more dense structure for the biased films, which correlated to the significantly lower film resistivity. In order to overcome deficiencies in sputtered silicon dioxide (SiO2) films the rf magnetron sputtering process was optimized by using a full factorial design of experiment (DOE). The optimized SiO2 film has a 5.7 MV/cm breakdown field and a 6.2 nm/min deposition rate at 10 W/cm2 RF power, 3 mTorr pressure, 300 °C substrate temperature, and 56 V substrate bias. Thin film transistors (TFTs) were also fabricated and characterized to show the prospective applications of the optimized SiO2 films. The effect that direct current (DC) substrate bias has on radio frequency (RF)-sputter-deposited amorphous silicon (a-Si) films was also investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFT) that were completely sputter-deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film. The crystallization properties of amorphous silicon (a-Si) thin film deposited by rf magnetron sputter deposition with substrate bias have been thoroughly characterized. The crystallization speed can be increased and the crystallization temperature can be drastically lowered relative to unbiased a-Si even though the stress state of biased a-Si film is highly compressive. The substrate bias enhances defect formation (vacancies, dislocations, stacking faults) via ion bombardment during the film growth, which effectively increases the driving force for crystallization of the films. The electrical and optical properties of sputter-deposited silicon nitride (SiNx) and n+ amorphous silicon (n+ a-Si) films as a function of substrate bias during sputter deposition were investigated. The breakdown voltage of sputter-deposited SiNx with 20 W (125 V) substrate bias is 7.65 MV/cm which is equivalent to that of plasma enhanced chemical vapor deposition (PECVD) SiNx films. The conductivity of n+ a-Si films are also enhanced by applying substrate bias during the sputter deposition. To verify the effect of substrate bias, amorphous silicon thin film transistors (TFTs) were fabricated with substrate biased thin films and compared their electrical properties with conventional sputter deposited TFTs. Lastly, electrochemical measurements were analyzed using gold and pyrrole solution to verify the active addressability of the TFT array fabricated by entirely by sputter deposited thin films below 200 °C temperature

GAS SENSING PROPERTIES AND TRANSPORT PROPERTIES OF MULTI WALLED CARBON NANOTUBES

Multi walled carbon nanotubes (MWCNT) grown in highly ordered porous alumina templates were incorporated into a resistive gas sensor design and were evaluated for their sensitivities. The material characteristics and electrical properties of the nanotubes were analyzed. A study was undertaken to elucidate the effect of UV light on desorption characteristics and the dependence of sensitivity on (i) thickness of amorphous carbon layers and (ii) flow rates of analyte gases. These sensors were highly responsive to both oxidizing and reducing gases with steady state sensitivities of 5% and 10% for 100ppm of NH3 and NO2 respectively, at room temperature. As part of a comparative study, thick films of MWCNTs grown on Si/SiO2 substrates were integrated into various nano-composite based sensors and were evaluated for their response. Steady state sensitivities as high as 10% and 11% were achieved for 100ppm of NH3 and NO2 respectively, at room temperature. MWCNTs were characterized for their electrical properties by I–V measurements at room temperatures. A typical I-V curve with an ohmic behavior was observed for a device with high work function metals (example: Au, Pt); Schottky behavior was observed for devices with metal contacts having low work functions (example: Al, Cu)

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors

abstract: Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm[superscript 2] and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate

Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C.

III-V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III-Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)-coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III-Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics

New Application for Indium Gallium Zinc Oxide thin film transistors: A fully integrated Active Matrix Electrowetting Microfluidic Platform

The characterization and fabrication of active matrix TFTs [Thin Film Transistors] have been studied for applying an addressable microfluidic electrowetting channel device. The a-IGZO [Amorphous Indium Gallium Zinc Oxide] is used for electronic switching device to control the microfluidic device because of its high mobility, transparency, and easy to fabrication. The purpose of this dissertation is to optimize each IGZO TFT process including the optimization of a-IGZO properties to achieve robust device for application. To drive the IGZO TFTs, the channel resistance of IGZO layer and contact resistance between IGZO layer and source/drain (S/D) electrode are discussed in this dissertation. In addition, the generalization of IGZO sputter condition is investigated by calculation of IGZO and O2 [Oxygen] incorporation rate at different oxygen partial pressure and different sputter targets. To develop the robust IGZO TFTs, the different passivation layers deposited by RF [Radio Frequency] magnetron sputter are investigated by comparing the electrical characteristics of TFTs. The effects PECVD [Plasma Enhanced Chemical Vapor Deposition] of SiO2 [Silicon Dioxide] passivation layers on IGZO TFTs is studied the role of hydrogen and oxygen with analyzed and compared the concentration by the SIMS [Secondary Ion Mass Spectroscopy]. In addition, the preliminary electrowetting tests are performed for electrowetting phenomena, the liquid droplet actuation, the comparison between conventional electrowetting and Laplace barrier electrowetting, and the different size electrode effect for high functional properties. The active matrix addressing method are introduced and investigated for driving the electrowetting microfluidic channel device by Pspice simulation. Finally, the high resolution electrowetting microfluidic device (16ⅹ16 matrix) is demonstrated by driving liquid droplet and channel moving using active matrix addressing method and fully integrated IGZO TFTs

Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of 5 V for several hours