Models for reducing power consumption in CPLD and FPGA devices

Usage of programmable logic devices PLD has increased in the latest years because of the ability to quickly implement complex types of electronic systems while reducing cost and time of synthesis. This technology enables dynamic reconfiguration of different applications according to specific requirements. Also, power consumption and its loss is becoming an increasingly important requirement in the design of systems for portable applications fed by batteries. Other factors to be taken into account in the consumption of power are elements that are used for manufacturing, packaging, and cooling systems. Power consumption must be taken into consideration especially for wireless applications where battery technologies provide power 20 W/h and voltage 1.2 volts. Despite improvements in battery technology, the development of methods for reducing power consumption plays a decisive role in portable applications. Therefore, modeling of power consumption has become a requirement with the highest impact in the performance of FPGA elements. Despite generated models of the different manufacturers of these elements, this article will appear comparisons of models based on experimental measurements performed on both CPLD and FPGA elements. Based on these models is selected to simulate a system that will be implemented in two elements and see how reduced power consumption, without affecting system performance. Experimental results show that FPGA elements have better performance and significantly reduce the power consumption

FPGA-based smart camera mote for pervasive wireless network

International audienceSmart camera networks raise challenging issues in many fields of research, including vision processing, communication protocols, distributed algorithms or power management. The ever increasing resolution of image sensors entails huge amounts of data, far exceeding the bandwidth of current networks and thus forcing smart camera nodes to process raw data into useful information. Consequently, on-board processing has become a key issue for the expansion of such networked systems. In this context, FPGA-based platforms, supporting massive, fine grain data parallelism, offer large opportunities. Besides, the concept of a middleware, providing services for networking, data transfer, dynamic loading or hardware abstraction, has emerged as a means of harnessing the hardware and software complexity of smart camera nodes. In this paper, we prospect the development of a new kind of smart cameras, wherein FPGAs provide high performance processing and general purpose processors support middleware services. In this approach, FPGA devices can be reconfigured at run-time through the network both from explicit user request and transparent middleware decision. An embedded real-time operating system is in charge of the communication layer, and thus can autonomously decide to use a part of the FPGA as an available processing resource. The classical programmability issue, a significant obstacle when dealing with FPGAs, is addressed by resorting to a domain specific high-level programming language (CAPH) for describing operations to be implemented on FPGAs

A Scalable Parallel Architecture with FPGA-Based Network Processor for Scientific Computing

This thesis discuss the design and the implementation of an FPGA-Based Network Processor for scientific computing, like Lattice Quantum ChromoDinamycs (LQCD) and fluid-dynamics applications based on Lattice Boltzmann Methods (LBM). State-of-the-art programs in this (and other similar) applications have a large degree of available parallelism, that can be easily exploited on massively parallel systems, provided the underlying communication network has not only high-bandwidth but also low-latency. I have designed in details, built and tested in hardware, firmware and software an implementation of a Network Processor, tailored for the most recent families of multi-core processors. The implementation has been developed on an FPGA device to easily interface the logic of NWP with the CPU I/O sub-system. In this work I have assessed several ways to move data between the main memory of the CPU and the I/O sub-system to exploit high data throughput and low latency, enabling the use of “Programmed Input Output” (PIO), “Direct Memory Access” (DMA) and “Write Combining” memory-settings. On the software side, I developed and test a device driver for the Linux operating system to access the NWP device, as well as a system library to efficiently access the network device from user-applications. This thesis demonstrates the feasibility of a network infrastructure that saturates the maximum bandwidth of the I/O sub-systems available on recent CPUs, and reduces communication latencies to values very close to those needed by the processor to move data across the chip boundary

Mobile Devices and Android Apps for Drug Administration to Patients with Parkinson’s Disease

Parkinsonova bolezen (PB) je nevrodegenerativna motnja, ki se pojavi po 60. letu starosti, pri nekaterih lahko tudi prej. Najbolj opazni in težki simptomi so tresavica, bradikinezija (počasno gibanje), togost in nestabilnost pacienta. Za PB znanost in medicina še nista odkrili zdravila, so pa na voljo terapije, ki pomagajo omiliti simptome, kot sta dopaminska terapija in globinska možganska stimulacija. Najbolj pogosta terapija med PB pacienti je dopaminska terapija, vendar ima tudi neprijetne stranske učinke, kot je disleksija: resnost stranskega učinka je odvisna od velikosti odmerka zdravila. Številne raziskave se ukvarjajo s problematiko disleksije, toda zelo malo se jih usmerja v osebnostni pristop k terapiji za PB. Ta raziskava je usmerjena v osebnostni pristop zdravljenja PB s pomočjo mobilnih in brezžičnih naprav za ocenitev resnosti simptomov PB ter primernega odmerka zdravila za pacienta s PB preko pritiska na ekran pametnega telefona. Aplicirani pritisk je preveden v analogni električni signal in nato v niz digitalnih podatkov, ki so s pomočjo CPLD-ja (Complex Programming Logic Device) poslani do pametnega telefona. Z aplikacijo, vključeno na androidnem operacijskem sistemu, so digitalni podatki obdelani preko različnih matematičnih funkcij: FFT (Fast Fourier Transformations), reakcijski čas in čas premikanja ter s prenosno funkcijo tretjega reda za izračun priporočljive količine zdravila. Raziskava obravnava tudi problematiko ustvarjanja novih prenosnih naprav, ki bi s svojo prisotnostjo na trgu prispevale k boljšemu zdravju prebivalstva, ter njihove prednosti in slabosti.Parkinson\u27s disease (PD) is neurodegenerative disorder, which usually occurs after the age of 60 and in some cases even earlier. One of the most notable and severe symptoms are tremor, bradykinesia (slow-movement), rigidity and postural instability. Medical sciences haven’t found a cure for the PD, however there are treatments like Dopamine treatment and Deep Brain Stimulation, which may alleviate the symptoms. The most frequently used Dopamine treatment, may have severe side effect, such as Dyskinesia, which brings new barrier into PD patients’ lives: the severity of Dyskinesia is related to the level of drug administration to PD patients. Various approaches to addressing Dyskinesia do exist, but none of them administers PD drugs according to individual patient needs. This research proposes the use of mobile and wireless hardware and software technologies for estimating the severity of PD symptoms, and administering PD drugs according to the measurements of PD patient’s pressures of his/her finger on the screen of a mobile device. This pressure, translated into analogue voltage, and digital bits, with the help of CPLD (Complex Programming Logic Device) is sent to a smart phone and taken by an App in the Android environment. The computations performed by the App will through FFT (Fast Fourier Transformations), Reaction time and Movement time calculate the severity of the PD symptoms and decide on the appropriate amount of drug administration for that patient, at the moment when the measurement has been taken. The novelty of the proposal is twofold. It allows a high level of personalisation in the PD treatment and uses the latest hardware and software technologies to bring new solution in the field of drug administration to PD patients. The research also debates the issue of creating new gadgets for pervasive healthcare, which is juxtaposed to the powerful Android operating environments and proliferation of smart phones. They can together challenge our need for developing more healthcare gadgets in future

The development of a node for a hardware reconfigurable parallel processor

This dissertation concerns the design and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic device and has high speed communications channels for inter-node communication. The design of the node provided high-speed serial communications channels allowing the implementation of various network topographies. The node also provided a PCI master interface to provide an external interface and communicate with local nodes on the bus. A high speed RlSC processor provided communication and system control functions and the reconfigurable logic device provided communication interfaces and data processing functions. The node was designed and implemented as a PCI card that interfaced a standard PCI bus. VHDL designs for logic devices that provided system support were developed, VHDL designs for the reconfigurable logic FPGA and software including drivers and system software were written for the node. The 64-bit version Linux operating system was then ported to the processor providing a UNIX environment for the system. The node functioned as specified and parallel and hardware accelerated processing was demonstrated. The hardware acceleration was shown to provide substantial performance benefits for the system

Seven strategies for tolerating highly defective fabrication

In this article we present an architecture that supports fine-grained sparing and resource matching. The base logic structure is a set of interconnected PLAs. The PLAs and their interconnections consist of large arrays of interchangeable nanowires, which serve as programmable product and sum terms and as programmable interconnect links. Each nanowire can have several defective programmable junctions. We can test nanowires for functionality and use only the subset that provides appropriate conductivity and electrical characteristics. We then perform a matching between nanowire junction programmability and application logic needs to use almost all the nanowires even though most of them have defective junctions. We employ seven high-level strategies to achieve this level of defect tolerance

FPGA BASED IMPLEMENTATION OF A POSITION ESTIMATOR FOR CONTROLLING A SWITCHED RELUCTANCE MOTOR

Rotor Position information is essential in the operation of the Switched Reluctance Motor (SRM) for properly controlling its phase currents. This thesis uses Field Programmable Gate Array (FPGA) technology to implement a method to estimate the SRMs rotor position using the inverse inductance value of the SRMs phases. The estimated rotor position is given as input to the Commutator circuit, also implemented in the FPGA, to determine when torque-producing currents should be input in the SRM phase windings. The Estimator and Commutator design is coded using Verilog HDL and is simulated using Xilinx tools. This circuit is implemented on a Xilinx Virtex XCV800 FPGA system. The experimentally generated output is validated by comparing it with simulation results from a Simulink model of the Estimator. The performance of the FPGA based SRM rotor position estimator in terms of calculation time is compared to a digital signal processor (DSP) implementation of the same position estimator algorithm. It is found that the FPGA rotor position Estimator with a 5MHz clock can update its rotor position estimate every 7s compared to an update time of 50s for a TMS320C6701-150 DSP implementation using a commercial DSP board. This is a greater than 7 to one reduction in the update time