Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

A Non-Blocking Design Paradigm for WDM Mesh Backbone Networks and Its Performance Analysis

Current network design problems can be solved by offline or online methods. Offline methods are criticized for their complexity and inflexibility, whereas online methods lack guaranteed optimality. Non-blocking properties, which are typically studied in switching structures, could be used to evaluate the capability of a switching structure to handle dynamic traffic. This dissertation extends the study of non-blocking networks to general-connected mesh WDM backbone networks. This study begins by finding that a set of special graphs have certain non-blocking properties, and that non-blocking routing algorithms can be designed to be implemented in a distributable manner without a central decision system. The in-depth philosophy of this research is to investigate the relationship among these non-blocking properties, the topography of the network, and the power of these distributed routing algorithms. This design paradigm is illustrated by applying it to a potential implementation for NSFNet. After confirming that NSFNet is NOT non-blocking, we propose a virtual topography that makes NSFNet virtually non-blocking, along with system diagrams for the node structures and the discussion of the implementation framework. To evaluate the performance of the non-blocking algorithms, we compare the performance of our proposed online algorithm with other algorithms in a general traffic scenario

A bibliography on parallel and vector numerical algorithms

This is a bibliography of numerical methods. It also includes a number of other references on machine architecture, programming language, and other topics of interest to scientific computing. Certain conference proceedings and anthologies which have been published in book form are listed also

Mathematical Methods and Operation Research in Logistics, Project Planning, and Scheduling

In the last decade, the Industrial Revolution 4.0 brought flexible supply chains and flexible design projects to the forefront. Nevertheless, the recent pandemic, the accompanying economic problems, and the resulting supply problems have further increased the role of logistics and supply chains. Therefore, planning and scheduling procedures that can respond flexibly to changed circumstances have become more valuable both in logistics and projects. There are already several competing criteria of project and logistic process planning and scheduling that need to be reconciled. At the same time, the COVID-19 pandemic has shown that even more emphasis needs to be placed on taking potential risks into account. Flexibility and resilience are emphasized in all decision-making processes, including the scheduling of logistic processes, activities, and projects

Numerical aerodynamic simulation facility feasibility study

There were three major issues examined in the feasibility study. First, the ability of the proposed system architecture to support the anticipated workload was evaluated. Second, the throughput of the computational engine (the flow model processor) was studied using real application programs. Third, the availability reliability, and maintainability of the system were modeled. The evaluations were based on the baseline systems. The results show that the implementation of the Numerical Aerodynamic Simulation Facility, in the form considered, would indeed be a feasible project with an acceptable level of risk. The technology required (both hardware and software) either already exists or, in the case of a few parts, is expected to be announced this year. Facets of the work described include the hardware configuration, software, user language, and fault tolerance

Models, Algorithms, and Architectures for Scalable Packet Classification

The growth and diversification of the Internet imposes increasing demands on the performance and functionality of network infrastructure. Routers, the devices responsible for the switch-ing and directing of traffic in the Internet, are being called upon to not only handle increased volumes of traffic at higher speeds, but also impose tighter security policies and provide support for a richer set of network services. This dissertation addresses the searching tasks performed by Internet routers in order to forward packets and apply network services to packets belonging to defined traffic flows. As these searching tasks must be performed for each packet traversing the router, the speed and scalability of the solutions to the route lookup and packet classification problems largely determine the realizable performance of the router, and hence the Internet as a whole. Despite the energetic attention of the academic and corporate research communities, there remains a need for search engines that scale to support faster communication links, larger route tables and filter sets and increasingly complex filters. The major contributions of this work include the design and analysis of a scalable hardware implementation of a Longest Prefix Matching (LPM) search engine for route lookup, a survey and taxonomy of packet classification techniques, a thorough analysis of packet classification filter sets, the design and analysis of a suite of performance evaluation tools for packet classification algorithms and devices, and a new packet classification algorithm that scales to support high-speed links and large filter sets classifying on additional packet fields

Techniques de routage pseudo-aléatoire pour une application micro-électronique

Résumé La problématique de routage est très actuelle. On en trouve des applications dans les GPS, les prévisions de trafic routier, mais aussi pour le prototypage sur FPGA, la fabrication de puces électroniques ou le trafic TCP/IP sur Internet. On trouve des publications sur le sujet depuis plusieurs dizaines d'années, mais on observe actuellement une recrudescence confirmant l'actualité, l'importance et la complexité de ce problème. Cette thèse concerne le routage et ses ressources pour une application dans un nouveau type de système micro-électronique, nommé le WaferBoardTM . Son noyau consiste en un circuit électronique intégré à l'échelle d'une tranche de silicium (wafer). Peu d'applications commerciales de la micro-électronique ont exploité ce niveau d'intégration. Ce système de prototypage rapide vise à réduire d'un ou deux ordres de grandeur le temps de développement de systèmes électroniques. Il nécessite un ensemble d'outils logiciel de support, dont un outil de routage très rapide, capable de produire des solutions valables en des temps de l'ordre de la minute, et de certaines fonctionnalités spécifiques, l'équilibrage de délai ou le reroutage à la volée, au sein d'une netlist déjà routée. La problématique de routage pour cette application peut être imagée comme suit. Étant donné un réseau routier régulier (les routes d’Amériques du Nord en version cartésienne par exemple) et 100,000 voitures au départ lundi à 8h a.m. dans tout le pays avec des sources et destinations très variées; calculer les chemins pour toutes les voitures de telle sorte qu'aucune ne prenne la même route dans la journée. Il est 7h59 a.m, vous avez 1 minute, et des ponts sont inaccessibles pour travaux, en voici la liste. Cet exemple simpliste donne une idée des ordres de grandeurs de la problématique de routage que l'on cherche à résoudre pour cette application. Un algorithme de routage prend en paramètres deux structures de données : un graphe (ou réseau d'interconnexions) constitué de n\oe{}uds (sommets) et d'arcsUn arc relie deux sommets du graphe, et une netlistDans ce contexte, un netlist réfère à une liste d'interconnexions entre composants, liste de n\oe{}uds électriques dont les points de départ et d'arrivée sont positionnés géographiquement. Ainsi, au lieu de voitures, il s'agit de router des signaux électriques dont les points de départ et d'arrivée sont dictés par la position des broches des composants placés sur le système de prototypage. Un réseau régulier maillé mufti-dimensionnel (plus généralement appelé « réseau d'interconnexions ») sert de réseau routier dont certaines routes sont défectueuses, des ponts inaccessibles. En effet, le réseau d'interconnexions est un circuit électronique intégré à l'échelle d'une tranche de silicium complète, ce qui implique la présence de défectuosités au sein de chaque circuit fabriqué. Contrairement aux circuits électroniques classiques, où chacun est testé et les défectueux écartés, une intégration à l'échelle de la tranche demande de fortes redondances au sein du circuit pour minimiser le taux de rejets. Pour l'application du WaferBoard, un certain nombre d'éléments du réseau d'interconnexions seront fort probablement défectueux sur chaque circuit produit; l'algorithme de routage se doit de prendre en compte ces éléments très particuliers. Cette contrainte ne se retrouve pas dans les applications plus classiques des routeurs que l'on retrouve dans les PCB, circuits FPGA ou circuits VLSI. D'autres contraintes s'appliquent à ce projet particulier : la latence induite par la technologie est environ un ordre de grandeur plus importante que celle dans les circuits sur PCB, ce qui impose un routage orienté vers sa réduction.----------Abstract The routing problem is very actual. Applications are found in GPS, road traffic forecast, but also for prototyping on FPGA, or TCP/IP traffic on the Internet. Publications on the subject have existed for several decades, but new publications keep appearing, confirming the importance and complexity of the problem. This thesis deals with routing and the resources it requires for a new category of micro-electronic applications, called the WaferBoard. It is an electronic circuit integrated at the wafer scale. Few commercial applications of micro-electronics have exploited this level of integration. This rapid prototyping system aims at reducing by one or two orders of magnitude the development time of digital circuits. It requires a very fast routing tool, capable of producing viable solutions in a few minutes, with dedicated functionality such as balancing delays and rerouting on the fly parts of a netlist. The routing problem for this application can be pictured as follows. Given a regular road network of the size of north america, if 100.000 cars were to start Monday 8 a.m. across the continent with a wide variety of sources and destinations; the challenge is to compute paths for all cars so none of them take the same route that day. It is 7:59 am, you have 1 minute, and some bridges are under road work: here is the list. This simplistic example gives an idea of the orders of magnitude of the problem that need to be solved for this application. A routing algorithm takes as input: a graph (or interconnection network) made of nodes and edges, and a netlst, a list of electrical nodes with starting and ending points physically placed. Therefore, instead of cars, the problem consists of routing electrical signals with points of departure and arrival dictated by the pin position of components placed on the prototyping system. A regular, multi-dimensional mesh (also called "interconnection network") serves as a road network, which contains defective roads and inaccessible bridges. Indeed, the interconnection network is an electronic circuit integrated across a full wafer, implying the presence of defects within each manufactured circuit. Unlike conventional electronic circuits, where each is tested and defective ones are set apart, wafer scale integrated applications require lots of redundancy in the circuit to minimize the rejection rate. In the WaferBoard, a number of elements of the interconnection network will be defective in each circuit; the routing algorithm must take into account these very specific elements. This constraint is not found in the classic applications of routers found in PCB, FPGA or VLSI circuits. Other restrictions apply to this particular project: the latency induced by the technology is about one order of magnitude greater than that in the circuits of PCBs, which requires a routing oriented towards computation time reduction. This constraint partly explains the network architecture used. Within the WaferIC, the shortest distance is not necessarily the one that offers the smallest latency. This property of the network complexifies the routing problem. Balancing delays within a group of arbitrary size nets is a necessary feature of the routing algorithm, and the difficulty is amplified by the computation time limit. Indeed, the interest of the application is to reduce the time for a user to test a circuit: the time of setup is extremely short, and estimated at a few minutes only

Research in progress in applied mathematics, numerical analysis, fluid mechanics, and computer science

This report summarizes research conducted at the Institute for Computer Applications in Science and Engineering in applied mathematics, fluid mechanics, and computer science during the period October 1, 1993 through March 31, 1994. The major categories of the current ICASE research program are: (1) applied and numerical mathematics, including numerical analysis and algorithm development; (2) theoretical and computational research in fluid mechanics in selected areas of interest to LaRC, including acoustics and combustion; (3) experimental research in transition and turbulence and aerodynamics involving LaRC facilities and scientists; and (4) computer science

Multilayer optimization in radio resource allocation for the packet transmission in wireless networks

Doutoramento em Engenharia ElectrotécnicaNa última década tem-se assistido a um crescimento exponencial das redes de comunicações sem fios, nomeadamente no que se refere a taxa de penetração do serviço prestado e na implementação de novas infra-estruturas em todo o globo. É ponto assente neste momento que esta tendência irá não só continuar como se fortalecer devido à convergência que é esperada entre as redes móveis sem fio e a disponibilização de serviços de banda larga para a rede Internet fixa, numa evolução para um paradigma de uma arquitectura integrada e baseada em serviços e aplicações IP. Por este motivo, as comunicações móveis sem fios irão ter um papel fundamental no desenvolvimento da sociedade de informação a médio e longo prazos. A estratégia seguida no projecto e implementação das redes móveis celulares da actual geração (2G e 3G) foi a da estratificação da sua arquitectura protocolar numa estrutura modular em camadas estanques, onde cada camada do modelo é responsável pela implementação de um conjunto de funcionalidades. Neste modelo a comunicação dá-se apenas entre camadas adjacentes através de primitivas de comunicação pré-estabelecidas. Este modelo de arquitectura resulta numa mais fácil implementação e introdução de novas funcionalidades na rede. Entretanto, o facto das camadas inferiores do modelo protocolar não utilizarem informação disponibilizada pelas camadas superiores, e vice-versa acarreta uma degradação no desempenho do sistema. Este paradigma é particularmente importante quando sistemas de antenas múltiplas são implementados (sistemas MIMO). Sistemas de antenas múltiplas introduzem um grau adicional de liberdade no que respeita a atribuição de recursos rádio: o domínio espacial. Contrariamente a atribuição de recursos no domínio do tempo e da frequência, no domínio espacial os recursos rádio mapeados no domínio espacial não podem ser assumidos como sendo completamente ortogonais, devido a interferência resultante do facto de vários terminais transmitirem no mesmo canal e/ou slots temporais mas em feixes espaciais diferentes. Sendo assim, a disponibilidade de informação relativa ao estado dos recursos rádio às camadas superiores do modelo protocolar é de fundamental importância na satisfação dos critérios de qualidade de serviço exigidos. Uma forma eficiente de gestão dos recursos rádio exige a implementação de algoritmos de agendamento de pacotes de baixo grau de complexidade, que definem os níveis de prioridade no acesso a esses recursos por base dos utilizadores com base na informação disponibilizada quer pelas camadas inferiores quer pelas camadas superiores do modelo. Este novo paradigma de comunicação, designado por cross-layer resulta na maximização da capacidade de transporte de dados por parte do canal rádio móvel, bem como a satisfação dos requisitos de qualidade de serviço derivados a partir da camada de aplicação do modelo. Na sua elaboração, procurou-se que o standard IEEE 802.16e, conhecido por Mobile WiMAX respeitasse as especificações associadas aos sistemas móveis celulares de quarta geração. A arquitectura escalonável, o baixo custo de implementação e as elevadas taxas de transmissão de dados resultam num processo de multiplexagem de dados e valores baixos no atraso decorrente da transmissão de pacotes, os quais são atributos fundamentais para a disponibilização de serviços de banda larga. Da mesma forma a comunicação orientada à comutação de pacotes, inenente na camada de acesso ao meio, é totalmente compatível com as exigências em termos da qualidade de serviço dessas aplicações. Sendo assim, o Mobile WiMAX parece satisfazer os requisitos exigentes das redes móveis de quarta geração. Nesta tese procede-se à investigação, projecto e implementação de algoritmos de encaminhamento de pacotes tendo em vista a eficiente gestão do conjunto de recursos rádio nos domínios do tempo, frequência e espacial das redes móveis celulares, tendo como caso prático as redes móveis celulares suportadas no standard IEEE802.16e. Os algoritmos propostos combinam métricas provenientes da camada física bem como os requisitos de qualidade de serviço das camadas superiores, de acordo com a arquitectura de redes baseadas no paradigma do cross-layer. O desempenho desses algoritmos é analisado a partir de simulações efectuadas por um simulador de sistema, numa plataforma que implementa as camadas física e de acesso ao meio do standard IEEE802.16e.In the last decade mobile wireless communications have witnessed an explosive growth in the user’s penetration rate and their widespread deployment around the globe. It is expected that this tendency will continue to increase with the convergence of fixed Internet wired networks with mobile ones and with the evolution to the full IP architecture paradigm. Therefore mobile wireless communications will be of paramount importance on the development of the information society of the near future. In particular a research topic of particular relevance in telecommunications nowadays is related to the design and implementation of mobile communication systems of 4th generation. 4G networks will be characterized by the support of multiple radio access technologies in a core network fully compliant with the Internet Protocol (all IP paradigm). Such networks will sustain the stringent quality of service (QoS) requirements and the expected high data rates from the type of multimedia applications to be available in the near future. The approach followed in the design and implementation of the mobile wireless networks of current generation (2G and 3G) has been the stratification of the architecture into a communication protocol model composed by a set of layers, in which each one encompasses some set of functionalities. In such protocol layered model, communications is only allowed between adjacent layers and through specific interface service points. This modular concept eases the implementation of new functionalities as the behaviour of each layer in the protocol stack is not affected by the others. However, the fact that lower layers in the protocol stack model do not utilize information available from upper layers, and vice versa, downgrades the performance achieved. This is particularly relevant if multiple antenna systems, in a MIMO (Multiple Input Multiple Output) configuration, are implemented. MIMO schemes introduce another degree of freedom for radio resource allocation: the space domain. Contrary to the time and frequency domains, radio resources mapped into the spatial domain cannot be assumed as completely orthogonal, due to the amount of interference resulting from users transmitting in the same frequency sub-channel and/or time slots but in different spatial beams. Therefore, the availability of information regarding the state of radio resources, from lower to upper layers, is of fundamental importance in the prosecution of the levels of QoS expected from those multimedia applications. In order to match applications requirements and the constraints of the mobile radio channel, in the last few years researches have proposed a new paradigm for the layered architecture for communications: the cross-layer design framework. In a general way, the cross-layer design paradigm refers to a protocol design in which the dependence between protocol layers is actively exploited, by breaking out the stringent rules which restrict the communication only between adjacent layers in the original reference model, and allowing direct interaction among different layers of the stack. An efficient management of the set of available radio resources demand for the implementation of efficient and low complexity packet schedulers which prioritize user’s transmissions according to inputs provided from lower as well as upper layers in the protocol stack, fully compliant with the cross-layer design paradigm. Specifically, efficiently designed packet schedulers for 4G networks should result in the maximization of the capacity available, through the consideration of the limitations imposed by the mobile radio channel and comply with the set of QoS requirements from the application layer. IEEE 802.16e standard, also named as Mobile WiMAX, seems to comply with the specifications of 4G mobile networks. The scalable architecture, low cost implementation and high data throughput, enable efficient data multiplexing and low data latency, which are attributes essential to enable broadband data services. Also, the connection oriented approach of Its medium access layer is fully compliant with the quality of service demands from such applications. Therefore, Mobile WiMAX seems to be a promising 4G mobile wireless networks candidate. In this thesis it is proposed the investigation, design and implementation of packet scheduling algorithms for the efficient management of the set of available radio resources, in time, frequency and spatial domains of the Mobile WiMAX networks. The proposed algorithms combine input metrics from physical layer and QoS requirements from upper layers, according to the crosslayer design paradigm. Proposed schedulers are evaluated by means of system level simulations, conducted in a system level simulation platform implementing the physical and medium access control layers of the IEEE802.16e standard