Xampling: Signal Acquisition and Processing in Union of Subspaces

We introduce Xampling, a unified framework for signal acquisition and processing of signals in a union of subspaces. The main functions of this framework are two. Analog compression that narrows down the input bandwidth prior to sampling with commercial devices. A nonlinear algorithm then detects the input subspace prior to conventional signal processing. A representative union model of spectrally-sparse signals serves as a test-case to study these Xampling functions. We adopt three metrics for the choice of analog compression: robustness to model mismatch, required hardware accuracy and software complexities. We conduct a comprehensive comparison between two sub-Nyquist acquisition strategies for spectrally-sparse signals, the random demodulator and the modulated wideband converter (MWC), in terms of these metrics and draw operative conclusions regarding the choice of analog compression. We then address lowrate signal processing and develop an algorithm for that purpose that enables convenient signal processing at sub-Nyquist rates from samples obtained by the MWC. We conclude by showing that a variety of other sampling approaches for different union classes fit nicely into our framework.Comment: 16 pages, 9 figures, submitted to IEEE for possible publicatio

RAPID CLOCK RECOVERY ALGORITHMS FOR DIGITAL MAGNETIC RECORDING AND DATA COMMUNICATIONS

SIGLEAvailable from British Library Document Supply Centre-DSC:DXN024293 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Synchronisation in sampled receivers for narrowband digital modulation schemes.

SIGLEAvailable from British Library Document Supply Centre- DSC:DXN0033576 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications

This thesis describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR circuits topologies were investigated in terms of architecture and speed. Based on the investigation, we proposed a new concept of quarter-rate (i.e. the clocking speed in the circuit is 2.5 GHz for 10 Gb/s data rate) and dual-loop topology which consists of phase-locked and frequency-locked loop. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. A new quarter-rate phase detector based on the non-linear early-late phase detector concept has been used to achieve the multi-Giga bit/s speed and to eliminate the need of the front-end data pre-processing (edge detecting) units usually associated with the conventional CDR circuits. An eight-stage differential ring oscillator running at 2.5 GHz frequency center was used for the voltage-controlled oscillator (VCO) to generate low-jitter multi-phase clock signals. The transistor level simulation results demonstrated excellent performances in term of locking speed and power consumption. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modelled at gate level using the Verilog-A language and time-domain simulated

Theory of phaselock techniques as applied to aerospace transponders

Phaselock techniques as applied to aerospace transponder

Carrier Synchronization in High Bit-Rate Optical Transmission Systems

In this dissertation, design of optical transmission systems with differential detection and coherent detection is briefly described. More over, algorithms for carrier synchronization and phase estimation with their implementation in high bit-rate optical transmission systems are proposed

Synchronization in all-digital QAM receivers

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field. A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market. Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation. Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection

Study of solid-state integrated microwave circuits Scientific report no. 2, 15 Dec. 1965 - 14 Mar. 1966

Frequency-modulation telemetry transmitter configurations for use in 1-GHZ to 2-GHZ FREQUENCY range - solid state integrated microwave circuit

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe