Impact of 3D IC on NoC Topologies: A Wire Delay Consideration

International audienceIn this paper, we perform an exploration of 3D NoC architectures through physical design implementation based on two tiers Tezzaron 3D technology. The 3D NoC partitioning is done by dividing the NoC's datapath component into two blocks placed in the two tiers. Two Stacked NoC architectures namely Stacked 3D-Mesh NoC and Stacked 2D-Hexagonal NoC developed based on this partitioning strategy are analyzed by comparing their performances with Stacked 2D-Mesh NoC and classical 2D- Mesh and 3D-Mesh NoC. In order to measure the impact of wire delay on performance, two technology libraries (130 nm and 45 nm) representing old and advanced technologies have been used for the performance analysis. Results from physical implementations show that in advanced technologies such as 45 nm and below, the performance of Stacked 2D NoC topologies with datapath partitioning method have better performances compared with traditional 2D/3D Mesh topologies and Stacked 3D Mesh topology. We advocate here that with stacking there is no need for 3D NoC topologies for advanced 2-tier 3D IC and this is also confirmed for multistage networks like butterfly

System-Level Thermal-Aware Design of 3D Multiprocessors with Inter-Tier Liquid Cooling

Rising chip temperatures and aggravated thermal reliability issues have characterized the emergence of 3D multiprocessor system-on-chips (3D-MPSoCs), necessitating the development of advanced cooling technologies. Microchannel based inter-tier liquid cooling of ICs has been envisaged as the most promising solution to this problem. A system-level thermal-aware design of electronic systems becomes imperative with the advent of these new cooling technologies, in order to preserve the reliable functioning of these ICs and effective management of the rising energy budgets of high-performance computing systems. This paper reviews the recent advances in the area of systemlevel thermal modeling and management techniques for 3D multiprocessors with advanced liquid cooling. These concepts are combined to present a vision of a green data center of the future which reduces the CO2 emissions by reusing the heat it generates

Thermo-Mechanical Effects Of Thermal Cycled Copper Through Silicon Vias

The semiconductor industry is currently facing transistor scaling issues due to fabrication thresholds and quantum effects. In this \u27More-Than-Moore\u27 era, the industry is developing new ways to increase device performance, such as stacking chips for three-dimensional integrated circuits (3D-IC). The 3D-IC\u27s superior performance over their 2D counterparts can be attributed to the use of vertical interconnects, or through silicon vias (TSV). These interconnects are much shorter, reducing signal delay. However TSVs are susceptible to various thermo-mechanical reliability concerns. Heating during fabrication and use, in conjunction with coefficient of thermal expansion mismatch between the copper TSVs and silicon substrate, create harmful stresses in the system. The purpose of this work is to evaluate the signal integrity of Cu-TSVs and determine the major contributing factors of the signal degradation upon in-use conditions. Two series of samples containing blind Cu-TSVs embedded in a Si substrate were studied, each having different types and amounts of voids from manufacturing. The samples were thermally cycled up to 2000 times using three maximum temperatures to simulate three unique in-use conditions. S11 parameter measurements were then conducted to determine the signal integrity of the TSVs. To investigate the internal response from cycling, a protocol was developed for cross-sectioning the copper TSVs. Voids were measured using scanning electron microscope and focused ion beam imaging of the cross-sections, while the microstructural evolution of the copper was monitored with electron backscattering diffraction. An increase in void area was found to occur after cycling. This is thought to be the major contributing factor in the signal degradation of the TSVs, since no microstructural changes were observed in the copper

Temperature-Aware Design and Management for 3D Multi-Core Architectures

Vertically-integrated 3D multiprocessors systems-on-chip (3D MPSoCs) provide the means to continue integrating more functionality within a unit area while enhancing manufacturing yields and runtime performance. However, 3D MPSoCs incur amplified thermal challenges that undermine the corresponding reliability. To address these issues, several advanced cooling technologies, alongside temperature-aware design-time optimizations and run-time management schemes have been proposed. In this monograph, we provide an overall survey on the recent advances in temperature-aware 3D MPSoC considerations. We explore the recent advanced cooling strategies, thermal modeling frameworks, design-time optimizations and run-time thermal management schemes that are primarily targeted for 3D MPSoCs. Our aim of proposing this survey is to provide a global perspective, highlighting the advancements and drawbacks on the recent state-of-the-ar

Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception.In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Approches d'optimisation et de personnalisation des réseaux sur puce (NoC : Networks on Chip)

Systems-on-chip (SoC) have become more and more complex due to the development of integrated circuit technology.Recent studies have shown that in order to improve the performance of a specific SoC application domain, the on-chipinter-connects (OCI) architecture must be customized at design-time or at run-time. Related approaches generallyprovide application-specific SoCs tailored to specific applications. The aim of this thesis is to carry out new approachesfor Network-on-Chip (NoC) and study their performances, especially in terms of latency, throughput, energyconsumption and simplicity of implementation.We have proposed an approach to allow designers to customize a candidate OCI architecture by adding strategiclinks in order to match large application workload. The analytical evaluation focuses on improving the physicalparameters of the NoC topology regardless of the application that should run on. The evaluation by simulationfocuses to evaluate the communication performances of the NoC. Simulations results show the effectiveness ofthis approach to improve the NoC performances. We have also introduced a compartmental Fluid-flow basedmodeling approach to allocate required resource for each buffer based on the application traffic pattern. Simulationsare conducted and results show the efficiency of this modeling method for a buffer space optimized allocation.Finally, we proposed a joint approach based on a system dynamics theory for evaluating the performance of a flowcontrol algorithm in NoCs. This algorithm allows NoC elements to dynamically adjust their inflow by using afeedback control-based mechanism. Analytical and simulation results showed the viability of this mechanism forcongestion avoidance in NoCs.Les systèmes embarqués sur puce (SoC : Systems-on-Chip) sont devenus de plus en plus complexes grâce à l’évolution de la technologie des circuits intégrés. Des études récentes ont montré que pour améliorer les performances du réseau su puce (NoC : Network-on-Chip), l’architecture de celui-ci pouvait être personnalisée, soit au moment de la conception, soit au moment de l’exécution. L’objectif principal de cette thèse est d’implémenter de nouvelles approches pour améliorer les performances des NoCs, notamment la latence, le débit, la consommation d’énergie, et la simplicité de mise en œuvre.Nous avons proposé une approche pour permettre aux concepteurs de personnaliser l'architecture d’un NoC par insertion de liens stratégiques, pour qu’elle soit adaptée à de nombreuses applications, sous la contrainte d’un budget limité en termes de nombre de liens. L’évaluation analytique porte sur l’amélioration des paramètres physiques de la topologie du NoC sans tenir compte de l’application qui devrait s’exécuter dessus. L’évaluation par simulation porte sur l’évaluation des performances de communication du NoC. Les résultats de simulations montrent l’efficacité de notre approche pour améliorer les performances du NoC. Nous avons également introduit une approche de modélisation par réseau à compartiments pour allouer les ressources nécessaires pour chaque tampon selon le modèle de trafic de l'application cible. Les résultats de simulations montrent l'efficacité de cette approche de modélisation pour l’allocation optimisée de l'espace tampon. Enfin, nous avons proposé une approche conjointe basée sur la théorie des systèmes dynamiques pour évaluer la performance d'un algorithme de contrôle de flux dans les NoCs. Cet algorithme permet aux éléments du NoC d’ajuster dynamiquement leur entrée en utilisant un mécanisme basé sur le contrôle de flux par rétroaction. Les résultats d’évaluations analytiques et de simulation montrent la viabilité de ce mécanisme pour éviter la congestion dans les NoCs