Performance evaluation of a linear predictor frequency estimator for mobile flat fading wireless channels

A well known frequency estimation algorithm using the linear prediction method is analyzed for flat fading wireless channels. The estimator outputs are statistically analyzed and its jitter performances are compared with the non-fading case and the Cramer-Rao bound. We provide a closed form solution for the distribution and the variance of the frequency estimates under fading conditions by making valid assumptions. We also verify the theoretical model using simulations. Analysis shows that the variance of the estimates for flat fading channels reaches a threshold point and increasing the transmit power does not necessarily improve the performances any further

Steady state distribution of a hyperbolic digital tanlock loop with extended pull-in range for frequency synchronization in high doppler environment

A hyperbolic arctan based Digital Tanlock Loop (D-TLL) operating with complex signals at base-band or intermediate frequencies in high Doppler environments is treated here. The arctan based loop, known as the tanlock loop (TLL), is used in software defined radio architectures for frequency acquisition and tracking. The hyperbolic nonlinearity intentionally introduced within the phase detector extends the pull-in range of the frequency for a given loop, compared to the normal D-TLL, allowing a wider frequency acquisition range which is suitable for high Doppler communications environment. In this paper we study the steady state phase noise performances of such a feedback loop for additive Gaussian noise using stochastic analysis. The stochastic model of a first-order hyperbolic loop and the theoretical analysis for the corresponding statistical distribution of the closed loop steady state phase noise are presented. The theoretical results are also verified by simulations

Bias-free phase tracking with linear and nonlinear systems

The arctan function is a well-known Maximum Likelihood (ML) estimator of the phase angle of a complex signal in additive white Gaussian noise. In this paper we revisit the arctan-based ML phase estimator and identify the bias problem for phase tracking. We show that the posteriori probability density function of becomes a bi-modal distribution for small values of signal to noise ratio and larger values of . In such cases the mean and the mode differ from each other, and as a result when such ML phase estimates are used as an input to a linear system (LS), example for phase tracking, the resulting output (which is essentially the mean value of the phase) differs from its true value which is the mode. In such situations there exist a mean (tracking) error at the output of the LS from its true value, and in (non-Bayesian) statistical terms there exist a bias in the estimates. In this paper, we provide some statistical analysis to explain the above problem, and also provide solutions for bias correction when a LS is used for tracking phase. Furthermore, we also provide two nonlinear phase tracking systems, 1) a Monte- Carlo based sequential phase tracking technique and 2) a secondorder digital-phase locked loop based method, for bias-free phase tracking which eliminate the bias problem that occurs in the case of linear phase tracking with ML estimates

A nonuniform DPLL architecture for optimized performance

This paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform-type digital phase-locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal-to-noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field-programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan.Published versio

A nonuniform DPLL architecture for optimized performance

This paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform-type digital phase-locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal-to-noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field-programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan.Published versio

Performance analysis of a logarithmic based phase detector for tan-locked loops

Nonlinear system design is a common practice in communication engineering for improved performances in advanced receivers. Here we look into a logarithmic based nonlinear loop for a second order arctan based digital phase locked loop (DPLL) for frequency synchronisation. The steady state and the acquisition performances of the loop are analyzed. The logarithmic nonlinearity is intentionally introduced to have improved phase noise performances during the steady state tracking mode. We present a close form expression for the open loop statistical distribution of the phase noise process and compare it with the linear PLL model on its performances. We also study the acquisition process of the loop by looking at the phase plane trajectories.5 page(s

Performance analysis of a logarithmic based phase detector for tan-locked loops

Nonlinear system design is a common practice in communication engineering for improved performances in advanced receivers. Here we look into a logarithmic based nonlinear loop for a second order arctan based digital phase locked loop (DPLL) for frequency synchronisation. The steady state and the acquisition performances of the loop are analyzed. The logarithmic nonlinearity is intentionally introduced to have improved phase noise performances during the steady state tracking mode. We present a close form expression for the open loop statistical distribution of the phase noise process and compare it with the linear PLL model on its performances. We also study the acquisition process of the loop by looking at the phase plane trajectories

Tanlock based loop with improved performance

This thesis is focused on the design, analysis, simulation and implementation of new improved architectures of the Time Delay Digital Tanlock Loop (TDTL) based digital phase-locked loop (DPLL). The proposed architectures overcome some fundamental limitations exhibited by the original TDTL. These limitations include the presence of nonlinearity in the phase detector (PD), the non-zero phase error of the first-order loop, the restricted locking range, particularly of the second-order loop, the limited acquisition speed and the noise performance. Two approaches were adopted in this work to alleviate these limitations: the first involved modifying the original TDTL through the incorporation of auxiliary circuit blocks that enhance its performance, whilst the second involved designing new tanlock-based architectures. The proposed architectures, which resulted from the above approaches, were tested under various input signal conditions and their performance was compared with the original TDTL. The proposed architectures demonstrated an improvement of up to fourfold in terms of the acquisition times, twofold in noise performance and a marked enhancement in the linearity and in the locking range. The effectiveness of the proposed tanlock-based architectures was also assessed and demonstrated by using them in various applications, which included FM demodulation, FM threshold extension, FM demodulation with improved THD (total harmonic distortion), and Doppler effect improvement. The results from these applications showed that the performance of the new architectures outperformed the original TDTL. Real-time performance of these architectures was evaluated through implementation of some of them on an FPGA (field-programmable gate array) based system. Practical results from the prototype FPGA based implementations confirmed the simulation results obtained from MATLAB/Simulink