Rendimiento del algoritmo AES sobre arquitecturas de memoria compartida

Actualmente AES (Advanced Encryption Standard) es uno de los algoritmos de cifrado simétrico más utilizados para encriptar información. El volumen de datos sensibles que se trasmiten en las redes se incrementa constantemente y cifrarlos puede requerir un tiempo significativo. Por lo anterior, es importante adaptar este algoritmo para aprovechar la potencia de cómputo de las arquitecturas paralelas emergentes. En este trabajo presentamos un análisis del rendimiento de AES sobre diversas arquitecturas de memoria compartida (multicore Intel E5- 2695v4, Xeon Phi 7230 y GPU Nvidia GTX 960), para datos de entrada de distinto tamaño. Los resultados revelan que la GPU es la mejor alternativa para cifrar datos de entrada que no superan los 32MB. Sin embargo, para un volumen mayor de datos, el multicore alcanza el mejor rendimiento, seguido por el Xeon Phi.XIX Workshop Procesamiento Distribuido y Paralelo (WPDP)Red de Universidades con Carreras en Informática (RedUNCI

Heterogeneous CPU/GPU Memory Hierarchy Analysis and Optimization

In this master thesis, we propose a scheduling reordering for heterogeneous processors based on a hysteresis detector to give some fairness and speedup to the memory request threads taking advantage of the bank level parallelism at the memory system organization

Exploiting heterogeneity in Chip-Multiprocessor Design

In the past decade, semiconductor manufacturers are persistent in building faster and smaller transistors in order to boost the processor performance as projected by Moore’s Law. Recently, as we enter the deep submicron regime, continuing the same processor development pace becomes an increasingly difficult issue due to constraints on power, temperature, and the scalability of transistors. To overcome these challenges, researchers propose several innovations at both architecture and device levels that are able to partially solve the problems. These diversities in processor architecture and manufacturing materials provide solutions to continuing Moore’s Law by effectively exploiting the heterogeneity, however, they also introduce a set of unprecedented challenges that have been rarely addressed in prior works. In this dissertation, we present a series of in-depth studies to comprehensively investigate the design and optimization of future multi-core and many-core platforms through exploiting heteroge-neities. First, we explore a large design space of heterogeneous chip multiprocessors by exploiting the architectural- and device-level heterogeneities, aiming to identify the optimal design patterns leading to attractive energy- and cost-efficiencies in the pre-silicon stage. After this high-level study, we pay specific attention to the architectural asymmetry, aiming at developing a heterogeneity-aware task scheduler to optimize the energy-efficiency on a given single-ISA heterogeneous multi-processor. An advanced statistical tool is employed to facilitate the algorithm development. In the third study, we shift our concentration to the device-level heterogeneity and propose to effectively leverage the advantages provided by different materials to solve the increasingly important reliability issue for future processors