Effective interprocess communication (IPC) in a real-time transputer network

The thesis describes the design and implementation of an interprocess communication (IPC) mechanism within a real-time distributed operating system kernel (RT-DOS) which is designed for a transputer-based network. The requirements of real-time operating systems are examined and existing design and implementation strategies are described. Particular attention is paid to one of the object-oriented techniques although it is concluded that these techniques are not feasible for the chosen implementation platform. Studies of a number of existing operating systems are reported. The choices for various aspects of operating system design and their influence on the IPC mechanism to be used are elucidated. The actual design choices are related to the real-time requirements and the implementation that has been adopted is described. [Continues.

Fabric-on-a-Chip: Toward Consolidating Packet Switching Functions on Silicon

The switching capacity of an Internet router is often dictated by the memory bandwidth required to bu¤er arriving packets. With the demand for greater capacity and improved service provisioning, inherent memory bandwidth limitations are encountered rendering input queued (IQ) switches and combined input and output queued (CIOQ) architectures more practical. Output-queued (OQ) switches, on the other hand, offer several highly desirable performance characteristics, including minimal average packet delay, controllable Quality of Service (QoS) provisioning and work-conservation under any admissible traffic conditions. However, the memory bandwidth requirements of such systems is O(NR), where N denotes the number of ports and R the data rate of each port. Clearly, for high port densities and data rates, this constraint dramatically limits the scalability of the switch. In an effort to retain the desirable attributes of output-queued switches, while significantly reducing the memory bandwidth requirements, distributed shared memory architectures, such as the parallel shared memory (PSM) switch/router, have recently received much attention. The principle advantage of the PSM architecture is derived from the use of slow-running memory units operating in parallel to distribute the memory bandwidth requirement. At the core of the PSM architecture is a memory management algorithm that determines, for each arriving packet, the memory unit in which it will be placed. However, to date, the computational complexity of this algorithm is O(N), thereby limiting the scalability of PSM switches. In an effort to overcome the scalability limitations, it is the goal of this dissertation to extend existing shared-memory architecture results while introducing the notion of Fabric on a Chip (FoC). In taking advantage of recent advancements in integrated circuit technologies, FoC aims to facilitate the consolidation of as many packet switching functions as possible on a single chip. Accordingly, this dissertation introduces a novel pipelined memory management algorithm, which plays a key role in the context of on-chip output- queued switch emulation. We discuss in detail the fundamental properties of the proposed scheme, along with hardware-based implementation results that illustrate its scalability and performance attributes. To complement the main effort and further support the notion of FoC, we provide performance analysis of output queued cell switches with heterogeneous traffic. The result is a flexible tool for obtaining bounds on the memory requirements in output queued switches under a wide range of tra¢ c scenarios. Additionally, we present a reconfigurable high-speed hardware architecture for real-time generation of packets for the various traffic scenarios. The work presented in this thesis aims at providing pragmatic foundations for designing next-generation, high-performance Internet switches and routers

Performance measurement and analysis of PC based cluster server using SET of Architecture and modeling a scalable High performance cluster

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A slotted-CDMA based wireless-ATM link layer : guaranteeing QoS over a wireless link.

Thesis (M.Sc.)-University of Natal, Durban, 2000.Future wireless networks will have to handle varying combinations of multimedia traffic that present the network with numerous quality of service (QoS) requirements. The continuously growing demand for mobile phones has resulted in radio spectrum becoming a precious resource that cannot be wasted. The current second-generation mobile networks are designed for voice communication and, even with the enhancements being implemented to accommodate data, they cannot efficiently handle the multimedia traffic demands that will be introduced in the near future. This thesis begins with a survey of existing wireless ATM (WATM) protocols, followed by an examination of some medium access control (MAC) protocols, supporting multimedia traffic, and based on code division multiple access (CDMA) physical layers. A WATM link layer protocol based on a CDMA physical layer, and incorporating techniques from some of the surveyed protocols, is then proposed. The MAC protocol supports a wide range of service requirements by utilising a flexible scheduling algorithm that takes advantage of the graceful degradation of CDMA with increasing user interference to schedule cells for transmission according to their maximum bit error rate (BER) requirements. The data link control (DLC) accommodates the various traffic types by allowing virtual channels (VCs) to make use of forward error correction (FEc) or retransmission techniques. The proposed link layer protocol has been implemented on a Blue Wave Systems DSP board that forms part of Alcatel Altech Telecoms' software radio platform. The details and practicality of the implementation are presented. A simulation model for the protocol has been developed using MIL3 's Opnet Modeler. Hence, both simulated and measured performance results are presented before the thesis concludes with suggestions for improvements and future work

Concurrent multipath transmission to improve performance for multi-homed devices in heterogeneous networks

Recent network technology developments have led to the emergence of a variety of access network technologies - such as IEEE 802.11, wireless local area network (WLAN), IEEE 802.16, Worldwide Interoperability for Microwave Access (WIMAX) and Long Term Evolution (LTE) - which can be integrated to offer ubiquitous access in a heterogeneous network environment. User devices also come equipped with multiple network interfaces to connect to the different network technologies, making it possible to establish multiple network paths between end hosts. However, the current connectivity settings confine the user devices to using a single network path at a time, leading to low utilization of the resources in a heterogeneous network and poor performance for demanding applications, such as high definition video streaming. The simultaneous use of multiple network interfaces, also called bandwidth aggregation, can increase application throughput and reduce the packets' end-to-end delays. However, multiple independent paths often have heterogeneous characteristics in terms of offered bandwidth, latency and loss rate, making it challenging to achieve efficient bandwidth aggregation. For instance, striping the flow's packets over multiple network paths with different latencies can cause packet reordering, which can significantly degrade performance of the current transport protocols. This thesis proposes three new solutions to mitigate the effects of network path heterogeneity on the performance of various concurrent multipath transmission settings. First, a network layer solution is proposed to stripe packets of delay-sensitive and high-bandwidth applications for concurrent transmission across multiple network paths. The solution leverages the paths' latency heterogeneity to reduce packet reordering, leading to minimal reordering delay, which improves performance of delay-sensitive applications. Second, multipath video streaming is developed for H.264 scalable video, where the reference video packets are adaptively assigned to low loss network paths to reduce drifting errors, thus combatting H.264 video distortion effectively. Finally, a new segment scheduling framework - which carefully considers path heterogeneity - is incorporated into the IETF Multipath TCP to improve throughput performance. The proposed solutions have been validated using a series of simulation experiments. The results reveal that the proposed solutions can enable efficient bandwidth aggregation for concurrent multipath transmission over heterogeneous network paths

3rd Many-core Applications Research Community (MARC) Symposium. (KIT Scientific Reports ; 7598)

This manuscript includes recent scientific work regarding the Intel Single Chip Cloud computer and describes approaches for novel approaches for programming and run-time organization

Design & Implementation of a Genetic Algorithm for scalable shortest path routing in SDN controllers

A method to calculate the Shortest Path in a Network using a Genetic Algorithm, enhanced with the use of a new multicore processor architecture: Epiphany. The study proposes an alternative algorithm that takes advantage fromf the scalable parallelism of these type of processor, and compares the performance with the classical Dijkstra algorithm outcome