15 research outputs found
Asynchronous techniques for new generation variation-tolerant FPGA
PhD ThesisThis thesis presents a practical scenario for asynchronous logic implementation that would benefit the modern Field-Programmable Gate Arrays (FPGAs) technology in improving reliability. A method based on Asynchronously-Assisted Logic (AAL) blocks is proposed here in order to provide the right degree of variation tolerance, preserve as much of the traditional FPGAs structure as possible, and make use of asynchrony only when necessary or beneficial for functionality. The newly proposed AAL introduces extra underlying hard-blocks that support asynchronous interaction only when needed and at minimum overhead. This has the potential to avoid the obstacles to the progress of asynchronous designs, particularly in terms of area and power overheads. The proposed approach provides a solution that is complementary to existing variation tolerance techniques such as the late-binding technique, but improves the reliability of the system as well as reducing the designâs margin headroom when implemented on programmable logic devices (PLDs) or FPGAs. The proposed method suggests the deployment of configurable AAL blocks to reinforce only the variation-critical paths (VCPs) with the help of variation maps, rather than re-mapping and re-routing. The layout level results for this method's worst case increase in the CLBâs overall size only of 6.3%. The proposed strategy retains the structure of the global interconnect resources that occupy the lionâs share of the modern FPGAâs soft fabric, and yet permits the dual-rail
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completion-detection (DR-CD) protocol without the need to globally double the interconnect resources. Simulation results of global and interconnect voltage variations demonstrate the robustness of the method
A formal study of two physical countermeasures against side channel attacks
Secure electronic circuits must implement countermeasures against a wide range of attacks.
Often, the protection against side channel attacks requires to be tightly integrated within the functionality to be protected.
It is now part of the designer\u27s job to implement them.
But this task is known to be error-prone, and with current development processes, countermeasures are evaluated often very late (at circuit fabrication).
In order to improve the confidence of the designer in the efficiency of the countermeasure,
we suggest in this article to resort to formal methods early in the design flow for two reasons.
First of all, we intend to check that the process of transformation of the design from the vulnerable description to the protected one does not alter the functionality.
Second, we wish to prove that the security properties (that can derive from a formal security functional specification) are indeed met after transformation.
Our first contribution is to show how such a framework can be setup (in COQ) for netlist-level protections.
The second contribution is to illustrate that this framework indeed allows to detect vulnerabilities in dual-rail logics,
with the examples of wave differential dynamic logic (WDDL) and balanced cell-based differential logic (BCDL)
Asynchrobatic logic for low-power VLSI design
In this work, Asynchrobatic Logic is presented. It is a novel low-power
design style that combines the energy saving benefits of asynchronous logic
and adiabatic logic to produce systems whose power dissipation is reduced in
several different ways. The term âAsynchrobaticâ is a new word that can be
used to describe these types of systems, and is derived from the
concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis
introduces the concept and theory behind Asynchrobatic Logic. It first
provides an introductory background to both underlying parent technologies
(asynchronous logic and adiabatic logic). The background material continues
with an explanation of a number of possible methods for designing complex
data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then
introduced as a comparison between asynchronous and Asynchrobatic buffer
chains, showing that for wide systems, it operates more efficiently. Two
more-complex sub-systems are presented, firstly a layout implementation of
the substitution boxes from the Twofish encryption algorithm, and secondly a
front-end only (without parasitic capacitances, resistances) simulation that
demonstrates a functional system capable of calculating the Greatest
Common Denominator (GCD) of a pair of 16-bit unsigned integers, which
under typical conditions on a 0.35ÎŒm process, executed a test vector requiring
twenty-four iterations in 2.067ÎŒs with a power consumption of 3.257nW.
These examples show that the concept of Asynchrobatic Logic has the
potential to be used in real-world applications, and is not just theory without
application. At the time of its first publication in 2004, Asynchrobatic Logic
was both unique and ground-breaking, as this was the first time that
consideration had been given to operating large-scale adiabatic logic in an
asynchronous fashion, and the first time that Asynchronous Stepwise
Charging (ASWC) had been used to drive an adiabatic data-path
Radio Communications
In the last decades the restless evolution of information and communication technologies (ICT) brought to a deep transformation of our habits. The growth of the Internet and the advances in hardware and software implementations modiïŹed our way to communicate and to share information. In this book, an overview of the major issues faced today by researchers in the ïŹeld of radio communications is given through 35 high quality chapters written by specialists working in universities and research centers all over the world. Various aspects will be deeply discussed: channel modeling, beamforming, multiple antennas, cooperative networks, opportunistic scheduling, advanced admission control, handover management, systems performance assessment, routing issues in mobility conditions, localization, web security. Advanced techniques for the radio resource management will be discussed both in single and multiple radio technologies; either in infrastructure, mesh or ad hoc networks
Computer Aided Verification
This open access two-volume set LNCS 10980 and 10981 constitutes the refereed proceedings of the 30th International Conference on Computer Aided Verification, CAV 2018, held in Oxford, UK, in July 2018. The 52 full and 13 tool papers presented together with 3 invited papers and 2 tutorials were carefully reviewed and selected from 215 submissions. The papers cover a wide range of topics and techniques, from algorithmic and logical foundations of verification to practical applications in distributed, networked, cyber-physical, and autonomous systems. They are organized in topical sections on model checking, program analysis using polyhedra, synthesis, learning, runtime verification, hybrid and timed systems, tools, probabilistic systems, static analysis, theory and security, SAT, SMT and decisions procedures, concurrency, and CPS, hardware, industrial applications
Telecommunications Networks
This book guides readers through the basics of rapidly emerging networks to more advanced concepts and future expectations of Telecommunications Networks. It identifies and examines the most pressing research issues in Telecommunications and it contains chapters written by leading researchers, academics and industry professionals. Telecommunications Networks - Current Status and Future Trends covers surveys of recent publications that investigate key areas of interest such as: IMS, eTOM, 3G/4G, optimization problems, modeling, simulation, quality of service, etc. This book, that is suitable for both PhD and master students, is organized into six sections: New Generation Networks, Quality of Services, Sensor Networks, Telecommunications, Traffic Engineering and Routing