High-Torque-Density Low-Cost Magnetic Gear Utilizing Hybrid Magnets and Advanced Materials

Two major challenges of existing high-performance magnetic gears are: (i) High content of rare-earth permanent magnets which results in high cost as well as price fluctuation; (ii) Conflict between mechanical and electromagnetic performances, especially in the design of highspeed rotor. A magnetic gear using a blend of magnet types, i.e NdFeB, or Dy-free NdFeB and ferrites, is proposed in this paper. The goal is to bring down the cost while retaining comparable torque-transducing performance to a baseline magnetic gear only using rare-earth NdFeB magnets. A variety of topologies based on different combinations of magnet types and geometric shapes have been studied and compared. In addition, the potential impact of using an advanced dual-phase material is evaluated. The goal is to eliminate the well-known tradeoff between rotor mechanical integrity and PM flux leakage

A comparative analysis and optimisation of thermo-mechanical energy storage technologies

Electrical Energy Storage (EES) can decouple energy production from its consumption and is urgently needed by both conventional energy system for load leveling and renewable energy system for intermittency smoothing. Currently, Pumped Hydro Energy Storage (PHES) and Compressed Air Energy Storage (CAES) are the main technologies employed, but they both suffer from high capital cost, geographical constraints and environmental issues. Therefore, many innovative concepts of EES technologies have been proposed recently, including the Adiabatic Compressed Air Energy Storage (A-CAES), Pumped Thermal Energy Storage (PTES), Isothermal Compressed Air Energy Storage (I-CAES) and Liquid Air Energy Storage (LAES). All of these EES store electricity in the forms of thermal or mechanical energy, and are most suitable for large-scale energy storage. As a result, they have received intensive treatment from both the industry and academia, but a comparative study and optimization of these large-scale thermo-mechanical energy storage systems from a thermo-economic perspective has so far been lacking, which forms the major part of this thesis. In this thesis, a complete set of system models have been developed for each EES technology, incorporating both thermodynamic and economic factors with due consideration for the constraints and variation ranges of each parameter. Then parametric studies are carried out for each system to analyze the impact of each parameter on the system performance (e.g., efficiency and unit cost). Loss and cost distributions are given for the representative cases, and the detailed explanation and potential improvement are also provided. After that, thermoeconomic optimizations are carried out for each individual system, and the trade-off between efficiency and unit cost as well as the main factors controlling this trade-off are revealed. Finally, these optimized systems are compared with each other, and new EES systems that combined the merits of existing ones are proposed as well. The results show that A-CAES and I-CAES tend to have higher system efficiency and lower unit cost than PTES and LAES, but the PTES and LAES enjoys higher energy density and more siting freedom. More information about the component efficiency and cost is required for an accurate comparison between A-CAES and I-CAES, and between PTES and LAES

Speed Binning Aware Design Methodology to Improve Profit under Parameter Variations

Abstract-Designin

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Closed-cycle gas dynamic laser design investigation

A conceptual design study was made of a closed cycle gas-dynamic laser to provide definition of the major components in the laser loop. The system potential application is for long range power transmission by way of high power laser beams to provide satellite propulsion energy for orbit changing or station keeping. A parametric cycle optimization was conducted to establish the thermodynamic requirements for the system components. A conceptual design was conducted of the closed cycle system and the individual components to define physical characteristics and establish the system size and weight. Technology confirmation experimental demonstration programs were outlined to develop, evaluate, and demonstrate the technology base needed for this closed cycle GDL system

Choose-Your-Own Adventure: A Lightweight, High-Performance Approach To Defect And Variation Mitigation In Reconfigurable Logic

For field-programmable gate arrays (FPGAs), fine-grained pre-computed alternative configurations, combined with simple test-based selection, produce limited per-chip specialization to counter yield loss, increased delay, and increased energy costs that come from fabrication defects and variation. This lightweight approach achieves much of the benefit of knowledge-based full specialization while reducing to practical, palatable levels the computational, testing, and load-time costs that obstruct the application of the knowledge-based approach. In practice this may more than double the power-limited computational capabilities of dies fabricated with 22nm technologies. Contributions of this work: • Choose-Your-own-Adventure (CYA), a novel, lightweight, scalable methodology to achieve defect and variation mitigation • Implementation of CYA, including preparatory components (generation of diverse alternative paths) and FPGA load-time components • Detailed performance characterization of CYA – Comparison to conventional loading and dynamic frequency and voltage scaling (DFVS) – Limit studies to characterize the quality of the CYA implementation and identify potential areas for further optimizatio

Controlling phonons and photons at the wavelength-scale: silicon photonics meets silicon phononics

Radio-frequency communication systems have long used bulk- and surface-acoustic-wave devices supporting ultrasonic mechanical waves to manipulate and sense signals. These devices have greatly improved our ability to process microwaves by interfacing them to orders-of-magnitude slower and lower loss mechanical fields. In parallel, long-distance communications have been dominated by low-loss infrared optical photons. As electrical signal processing and transmission approaches physical limits imposed by energy dissipation, optical links are now being actively considered for mobile and cloud technologies. Thus there is a strong driver for wavelength-scale mechanical wave or "phononic" circuitry fabricated by scalable semiconductor processes. With the advent of these circuits, new micro- and nanostructures that combine electrical, optical and mechanical elements have emerged. In these devices, such as optomechanical waveguides and resonators, optical photons and gigahertz phonons are ideally matched to one another as both have wavelengths on the order of micrometers. The development of phononic circuits has thus emerged as a vibrant field of research pursued for optical signal processing and sensing applications as well as emerging quantum technologies. In this review, we discuss the key physics and figures of merit underpinning this field. We also summarize the state of the art in nanoscale electro- and optomechanical systems with a focus on scalable platforms such as silicon. Finally, we give perspectives on what these new systems may bring and what challenges they face in the coming years. In particular, we believe hybrid electro- and optomechanical devices incorporating highly coherent and compact mechanical elements on a chip have significant untapped potential for electro-optic modulation, quantum microwave-to-optical photon conversion, sensing and microwave signal processing.Comment: 26 pages, 5 figure