Addressing the Smart Systems Design Challenge: The SMAC Platform

This article presents the concepts, the organization, and the preliminary application results of SMAC, a smart systems co-design platform. The SMAC platform, which has been developed as Integrated Project (IP) of the 7th ICT Call under the Objective 3.2 \u201cSmart components and Smart Systems integration\u201d addresses the challenges of the integration of heterogeneous and conflicting domains that emerge in the design of smart systems. SMAC includes methodologies and EDA tools enabling multi-disciplinary and multi-scale modelling and design, simulation of multidomain systems, subsystems and components at different levels of abstraction, system integration and exploration for optimization of functional and non-functional metrics. The article presents the preliminary results obtained by adopting the SMAC platform for the design of a limb tracking smart system

EOOLT 2007 – Proceedings of the 1st International Workshop on Equation-Based Object-Oriented Languages and Tools

Computer aided modeling and simulation of complex systems, using components from multiple application domains, such as electrical, mechanical, hydraulic, control, etc., have in recent years witness0065d a significant growth of interest. In the last decade, novel equation-based object-oriented (EOO) modeling languages, (e.g. Mode- lica, gPROMS, and VHDL-AMS) based on acausal modeling using equations have appeared. Using such languages, it has become possible to model complex systems covering multiple application domains at a high level of abstraction through reusable model components. The interest in EOO languages and tools is rapidly growing in the industry because of their increasing importance in modeling, simulation, and specification of complex systems. There exist several different EOO language communities today that grew out of different application areas (multi-body system dynamics, electronic circuit simula- tion, chemical process engineering). The members of these disparate communities rarely talk to each other in spite of the similarities of their modeling and simulation needs. The EOOLT workshop series aims at bringing these different communities together to discuss their common needs and goals as well as the algorithms and tools that best support them. Despite the short deadlines and the fact that this is a new not very established workshop series, there was a good response to the call-for-papers. Thirteen papers and one presentation were accepted to the workshop program. All papers were subject to reviews by the program committee, and are present in these electronic proceedings. The workshop program started with a welcome and introduction to the area of equa- tion-based object-oriented languages, followed by paper presentations and discussion sessions after presentations of each set of related papers. On behalf of the program committee, the Program Chairmen would like to thank all those who submitted papers to EOOLT'2007. Special thanks go to David Broman who created the web page and helped with organization of the workshop. Many thanks to the program committee for reviewing the papers. EOOLT'2007 was hosted by the Technical University of Berlin, in conjunction with the ECOOP'2007 conference

Automatic synthesis and optimization of floating point hardware.

Ho Chun Hok.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 74-78).Abstracts in English and Chinese.Abstract --- p.iiAcknowledgement --- p.vChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Aims --- p.3Chapter 1.3 --- Contributions --- p.3Chapter 1.4 --- Thesis Organization --- p.4Chapter 2 --- Background and Literature Review --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- Field Programmable Gate Arrays --- p.5Chapter 2.3 --- Traditional design flow and VHDL --- p.6Chapter 2.4 --- Single Description for Hardware-Software Systems --- p.7Chapter 2.5 --- Parameterized Floating Point Arithmetic Implementation --- p.8Chapter 2.6 --- Function Approximations by Table Lookup and Addition --- p.9Chapter 2.7 --- Summary --- p.10Chapter 3 --- Floating Point Arithmetic --- p.11Chapter 3.1 --- Introduction --- p.11Chapter 3.2 --- Floating Point Number Representation --- p.11Chapter 3.3 --- Rounding Error --- p.12Chapter 3.4 --- Floating Point Number Arithmetic --- p.14Chapter 3.4.1 --- Addition and Subtraction --- p.14Chapter 3.4.2 --- Multiplication --- p.17Chapter 3.5 --- Summary --- p.17Chapter 4 --- FLY - Hardware Compiler --- p.18Chapter 4.1 --- Introduction --- p.18Chapter 4.2 --- The Fly Programming Language --- p.18Chapter 4.3 --- Implementation details --- p.19Chapter 4.3.1 --- Compilation Technique --- p.19Chapter 4.3.2 --- Statement --- p.21Chapter 4.3.3 --- Assignment --- p.21Chapter 4.3.4 --- Conditional Branch --- p.22Chapter 4.3.5 --- While --- p.22Chapter 4.3.6 --- Parallel Statement --- p.22Chapter 4.4 --- Development Environment --- p.24Chapter 4.4.1 --- From Fly to Bitstream --- p.24Chapter 4.4.2 --- Host Interface --- p.24Chapter 4.5 --- Summary --- p.26Chapter 5 --- Float - Floating Point Design Environment --- p.27Chapter 5.1 --- Introduction --- p.27Chapter 5.2 --- Floating Point Tools --- p.28Chapter 5.2.1 --- Float Class --- p.29Chapter 5.2.2 --- Optimization --- p.31Chapter 5.3 --- Digital Sine-Cosine Generator --- p.33Chapter 5.4 --- VHDL Floating Point operator generator --- p.35Chapter 5.4.1 --- Floating Point Multiplier Module --- p.35Chapter 5.4.2 --- Floating Point Adder Module --- p.36Chapter 5.5 --- Application to Solving Differential Equations --- p.38Chapter 5.6 --- Summary --- p.40Chapter 6 --- Function Approximation using Lookup Table --- p.42Chapter 6.1 --- Table Lookup Approximations --- p.42Chapter 6.1.1 --- Taylor Expansion --- p.42Chapter 6.1.2 --- Symmetric Bipartite Table Method (SBTM) --- p.43Chapter 6.1.3 --- Symmetric Table Addition Method (STAM) --- p.45Chapter 6.1.4 --- Input Range Scaling --- p.46Chapter 6.2 --- VHDL Extension --- p.47Chapter 6.3 --- Floating Point Extension --- p.49Chapter 6.4 --- The N-body Problem --- p.52Chapter 6.5 --- Implementation --- p.54Chapter 6.6 --- Summary --- p.56Chapter 7 --- Results --- p.58Chapter 7.1 --- Introduction --- p.58Chapter 7.2 --- GCD coprocessor --- p.58Chapter 7.3 --- Floating Point Module Library --- p.59Chapter 7.4 --- Digital sine-cosine generator (DSCG) --- p.60Chapter 7.5 --- Optimization --- p.62Chapter 7.6 --- Ordinary Differential Equation (ODE) --- p.63Chapter 7.7 --- N Body Problem Simulation (Nbody) --- p.63Chapter 7.8 --- Summary --- p.64Chapter 8 --- Conclusion --- p.66Chapter 8.1 --- Future Work --- p.68Chapter A --- Fly Formal Grammar --- p.70Chapter B --- Original Fly Source Code --- p.71Bibliography --- p.7

Methoden und Beschreibungssprachen zur Modellierung und Verifikation vonSchaltungen und Systemen: MBMV 2015 - Tagungsband, Chemnitz, 03. - 04. März 2015

Der Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) findet nun schon zum 18. mal statt. Ausrichter sind in diesem Jahr die Professur Schaltkreis- und Systementwurf der Technischen Universität Chemnitz und das Steinbeis-Forschungszentrum Systementwurf und Test. Der Workshop hat es sich zum Ziel gesetzt, neueste Trends, Ergebnisse und aktuelle Probleme auf dem Gebiet der Methoden zur Modellierung und Verifikation sowie der Beschreibungssprachen digitaler, analoger und Mixed-Signal-Schaltungen zu diskutieren. Er soll somit ein Forum zum Ideenaustausch sein. Weiterhin bietet der Workshop eine Plattform für den Austausch zwischen Forschung und Industrie sowie zur Pflege bestehender und zur Knüpfung neuer Kontakte. Jungen Wissenschaftlern erlaubt er, ihre Ideen und Ansätze einem breiten Publikum aus Wissenschaft und Wirtschaft zu präsentieren und im Rahmen der Veranstaltung auch fundiert zu diskutieren. Sein langjähriges Bestehen hat ihn zu einer festen Größe in vielen Veranstaltungskalendern gemacht. Traditionell sind auch die Treffen der ITGFachgruppen an den Workshop angegliedert. In diesem Jahr nutzen zwei im Rahmen der InnoProfile-Transfer-Initiative durch das Bundesministerium für Bildung und Forschung geförderte Projekte den Workshop, um in zwei eigenen Tracks ihre Forschungsergebnisse einem breiten Publikum zu präsentieren. Vertreter der Projekte Generische Plattform für Systemzuverlässigkeit und Verifikation (GPZV) und GINKO - Generische Infrastruktur zur nahtlosen energetischen Kopplung von Elektrofahrzeugen stellen Teile ihrer gegenwärtigen Arbeiten vor. Dies bereichert denWorkshop durch zusätzliche Themenschwerpunkte und bietet eine wertvolle Ergänzung zu den Beiträgen der Autoren. [... aus dem Vorwort

Doctor of Philosophy

dissertationOver the last decade, cyber-physical systems (CPSs) have seen significant applications in many safety-critical areas, such as autonomous automotive systems, automatic pilot avionics, wireless sensor networks, etc. A Cps uses networked embedded computers to monitor and control physical processes. The motivating example for this dissertation is the use of fault- tolerant routing protocol for a Network-on-Chip (NoC) architecture that connects electronic control units (Ecus) to regulate sensors and actuators in a vehicle. With a network allowing Ecus to communicate with each other, it is possible for them to share processing power to improve performance. In addition, networked Ecus enable flexible mapping to physical processes (e.g., sensors, actuators), which increases resilience to Ecu failures by reassigning physical processes to spare Ecus. For the on-chip routing protocol, the ability to tolerate network faults is important for hardware reconfiguration to maintain the normal operation of a system. Adding a fault-tolerance feature in a routing protocol, however, increases its design complexity, making it prone to many functional problems. Formal verification techniques are therefore needed to verify its correctness. This dissertation proposes a link-fault-tolerant, multiflit wormhole routing algorithm, and its formal modeling and verification using two different methodologies. An improvement upon the previously published fault-tolerant routing algorithm, a link-fault routing algorithm is proposed to relax the unrealistic node-fault assumptions of these algorithms, while avoiding deadlock conservatively by appropriately dropping network packets. This routing algorithm, together with its routing architecture, is then modeled in a process-algebra language LNT, and compositional verification techniques are used to verify its key functional properties. As a comparison, it is modeled using channel-level VHDL which is compiled to labeled Petri-nets (LPNs). Algorithms for a partial order reduction method on LPNs are given. An optimal result is obtained from heuristics that trace back on LPNs to find causally related enabled predecessor transitions. Key observations are made from the comparison between these two verification methodologies

Definition and design of a new communication protocol and interfaces for data transmission in High Energy Physics experiments

High Energy Physics experiments have very similar architectures with respect to systems for acquisition of data from sensors and for control and management of the detector, and therefore similar requirements about data rate, trigger latency, robustness of critical data against transmission errors, radiation hardness and power dissipation and of hardware components and material budget. The use of common solutions that can be reused in different applicative contexts can reduce costs, risks and time needed for the development of new experiments. In particular, a research and development activity appeared as useful in the field of electrical links that are employed for data transmission to and from Front End circuits inside the detectors to move power-consuming optical converters away from the interaction point. Moving from these considerations, the FF-LYNX (Fast and Flexible links) project was started in January 2009 by a collaboration between INFN-PI (Italian National Institute for Nuclear Physics, division of Pisa) and the Department of Information Engineering (DII_IET) of the University of Pisa, with the aim of defining a new serial communication protocol for integrated distribution of TTC signals and Data Acquisition, satisfying the typical requirements of HEP applications and providing flexibility for its adaptation to different scenarios, and of its implementation in radiation-tolerant, low power interfaces. The work presented in this thesis constituted a phase of the FF-LYNX project working plan and was carried out at the Pisa division of INFN: in particular, it dealt with the definition of a first version of the FF-LYNX protocol and the design of hardware transmitter and receiver interfaces implementing it. In this thesis first of all the purposes of the project are presented and the methodology defined for the project work is outlined; then the FF-LYNX protocol (version 1) is described: the basic issues about trigger and data transmission that were considered in the definition of this version of the protocol are outlined, as well as the solutions that were adopted to address these issues, and the results of simulations in a high-level model of the link, intended to estimate various aspects of the protocol performance, are presented. Subsequently, the architecture that was defined for the interfaces implementing the FF-LYNX protocol version 1 is illustrated, and the VHDL models of the transmitter and receiver blocks that was created in the design phase of the FF-LYNX interfaces is described in detail also reporting results of simulations on a VHDL test bench for the complete transmitter-receiver system. Finally, an FPGA based emulator for the FF-LYNX transmitter-receiver system, foreseen as the final result for the FF-LYNX project first year of activity, is outlined in its functional architecture, the development board chosen for its implementation is briefly described, and the results of preliminary synthesis trials of the designed TX and RX blocks onto the target FPGA are reported

An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that functional languages are especially suitable for implementation of domain-specific languages, including HDLs. Casestudies examining the implementation complexity of HEP-specific language extensions to the functional HDCaml HDL will prove the viability of the suggested approach

Loop Transformations for the Optimized Generation of Reconfigurable Hardware

Current high-level design environments offer little support to implement data-intensive applications on heterogeneous-memory systems; they rather focus on parallelism. This thesis addresses the memory hierarchy problem to high-level transformations of loop structures. The composition of long transformation sequences by combining shorter subsequences is studied together with the influence of the order of applying transformation steps. Several methods are presented to estimate bounds on Ehrhart quasi-polynomials, which can be used to statically evaluate program properties, such as memory usage. Since loop transformations not only influence the data access pattern but also the control complexity we present a hardware loop controller architecture which supports hardware generation from the polyhedral representation used for loop transformations. The techniques are demonstrated by the semi-automatic generation of an FPGA implementation of an inverse discrete wavelet transform