Satellite-matrix-switched, time-division-multiple-access network simulator

A versatile experimental Ka-band network simulator has been implemented at the NASA Lewis Research Center to demonstrate and evaluate a satellite-matrix-switched, time-division-multiple-access (SMS-TDMA) network and to evaluate future digital ground terminals and radiofrequency (RF) components. The simulator was implemented by using proof-of-concept RF components developed under NASA contracts and digital ground terminal and link simulation hardware developed at Lewis. This simulator provides many unique capabilities such as satellite range delay and variation simulation and rain fade simulation. All network parameters (e.g., signal-to-noise ratio, satellite range variation rate, burst density, and rain fade) are controlled and monitored by a central computer. The simulator is presently configured as a three-ground-terminal SMS-TDMA network

Design for Testability in a SerDes System

Testing an IC after fabrication helps ensure chip functionality. The techniques that consider the creation and utilization of tests inside the design flow are called Design for Testability. The present work evaluates and improves the test modules implementing BIST techniques created by César Limones 2016 thesis. It is important to mention that this work reports the first effort to make the full SerDes analog and digital module integration at ITESO. It required all the designers to work together in order to complete the SerDes chip design flow. In particular, the comparison data module design structure was redefined after the data flow was analyzed. The test modules simulation demonstrated the correct functionality while the timing reports with a 156.25MHz clock frequency, showed that the design is timing compliant. The SerDes final layout, which also integrated the test modules, was created with the analog modules placement and routing. However, there were issues with the routing over the analog modules, which produced an overlap on the internal metal layers. For this reason, it is encouraged to further research about the association and outcomes between the layout of the analog modules, the LEF file generation, and the analog module routing in the design flowRealizar pruebas en un chip luego de ser fabricado asegura la funcionalidad del circuito integrado. Las técnicas que contemplan la creación y aplicación de pruebas dentro del flujo de diseño del chip se llaman design for testability (diseño testable). Esta tesina evalúa y mejora los módulos de prueba que implementan técnicas de BIST, los cuales fueron creados por César Limones en la tesina del 2016. Es importante mencionar que este trabajo reporta los primeros esfuerzos realizados en el ITESO en integrar los módulos análogos y digitales que componen el SerDes. Se requirió del trabajo conjunto de todos los diseñadores para completar el flujo de diseño del chip del SerDes. En particular, la estructura del módulo de comparación fue totalmente modificada luego de que el flujo de datos fue analizado. Mediante la simulación de los módulos pruebas se demostró su correcto funcionamiento y los reportes de análisis de tiempo aplicados con un reloj a una frecuencia de 156.25MHz, mostraron que el diseño cumple con las restricciones de tiempo. El layout (diseño) final del SerDes, que integra también los módulos de pruebas, fue creado con la colocación y enrutamiento de los módulos análogos. Sin embargo, se presentaron problemas con el enrutamiento creado sobre el módulo análogo lo cual provocó un solapamiento con las capas de metal internas. Por esta razón, se exhorta a investigar sobre la asociación y resultados entre el layout de los módulos análogos, la generación del archivo LEF y el enrutamiento de los módulos análogos en el flujo de diseño.ITESO, A. C.Consejo Nacional de Ciencia y Tecnologí

An RF BIST Architecture for Output Stages of Multistandard Radios

Article accepté pour publicationInternational audienceSoftware defined radios (SDR) platforms are in-creasingly complex systems which combine great flexibility and high performance. These two characteristics, together with highly integrated architectures make production test a challenging task. In this paper, we introduce an Radio Frequency (RF) Built-in Self-Test (BIST) strategy based on Periodically Nonuniform Sampling of the signal at the output stages of multistandard radios. We leverage the I/Q ADC channels and the DSP resources to extract the bandpass waveform at the output of the power amplifier (PA). Analytical expressions and simulations show that our time-interleaved conversion scheme is sensitive to time-skew. We show a time-skew estimation technique that allows us to surmount this obstacle. Simulation results show that we can effectively reconstruct the bandpass signal of the output stage using this architecture, opening the way for a complete RF BIST strategy for multistandard radios. Future developments will be focused on an efficient mapping to hardware of our new time-skew estimation for TIADC bandpass conversion

In-field Built-in Self-test for Measuring RF Transmitter Power and Gain

abstract: RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). However, this conversion circuitry is subject to similar process, voltage, and temperature (PVT) variations as the DUT and affects the measurement accuracy. So, it is important to monitor BIST performance over time, voltage and temperature, such that accurate in-field measurements can be performed. In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

Fast jitter tolerance testing for high-speed serial links in post-silicon validation

Post-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market (TTM) commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter (Tx) circuitry in real system environments. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature (PVT) test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3.ITESO, A.C

Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision