Adaptive Spread Spectrum Clock Generator using Delta-Sigma Digital-to-Time Converter

修士論

Variable Spurious Noise Mitigation Techniques in Hysteretic Buck Converters

This work proposes a current-mode hysteretic buck converter with a spur-free constant-cycle frequency-hopping controller that fully eliminates spurs from the switching noise spectrum irrespective of variations in the switching frequency and operating conditions. As a result, the need for frequency regulation loops to ensure non-varying switching frequency (i.e. fixed spurs location) in hysteretic controllers is eliminated. Moreover, compared to frequency regulation loops, the proposed converter offers the advantage of eliminating mixing and interference altogether due to its spur-free operation, and thus, it can be used to power, or to be integrated within noise-sensitive systems while benefiting from the superior dynamic performance of its hysteretic operation. The proposed converter uses dual-sided hysteretic band modulation to eliminate the inductor current imbalance that results from frequency hopping along with the output voltage transients and low-frequency noise floor peaking associated with it. Moreover, a feedforward adaptive hysteretic band controller is proposed to reduce variations in the switching frequency with the input voltage, and an all-digital soft-startup circuit is proposed to control the in-rush current without requiring any off-chip components. The converter is implemented in a 0.35-õm standard CMOS technology and it achieves 92% peak efficiency

Implementation of PWM Based Firing Scheme for Multilevel Inverters Using Microcontroller

The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Inverters can be broadly classified into single level inverter and multilevel inverter. Multilevel inverter as compared to single level inverters have advantages like minimum harmonic distortion, reduced EMI/RFI generation and can operate on several voltage levels. A multi-stage inverter is being utilized for multipurpose applications, such as active power filters, static var compensators and machine drives for sinusoidal and trapezoidal current applications. The drawbacks are the isolated power supplies required for each one of the stages of the multiconverter and it’s also lot harder to build, more expensive, harder to control in software. This project aims at generation of carrier based PWM scheme using POD strategy through the means of an AT89C51 microcontroller. The salient features are: Firstly, Both the high frequency triangular carrier wave and the sinusoidal reference signal are being generated in the microcontroller. The digital to analog converter(DAC0808)is then employed for converting them into their analog signal forms An opamp based comparator then compares these two carrier & reference signals to give us the desired sinusoidal pulse width modulated signal as the required final-output. The PWM signal thus generated is then used as triggering pulses for the multilevel inverters

Optimization of System Identification for Multi-Rail DC-DC Power Converters

Ph. D. Thesis.There have been many recursive algorithms investigated and introduced in real time parameter estimation of Switch Mode Power Converters (SMPCs) to improve estimation performance in terms of faster convergence speed, lower computational cost and higher estimation accuracy. These algorithms, including Dichotomous Coordinate Descent (DCD) - Recursive Least Square (RLS), Kalman Filter (KF) and Fast Affine Projection (FAP), etc., are commonly applied for performance comparison of system identification of single-rail power converters. When they need to be used in multi-rail architectures with a single centralized controller, the computational burden on the processor becomes significant. Typically, the computational effort is directly proportional to the number of converters/rails. This thesis presents an iterative decimation approach to significantly alleviate the computational burden of centralized controllers applying real-time recursive system identification algorithms in multirail power converters. The proposed approach uses a flexible and adjustable update rate rather than a fixed rate, as opposed to conventional adaptive filters. In addition, the step size/forgetting factors are varied, as well, corresponding to different iteration stages. As a result, reduced computational burden and faster model update can be achieved. Recursive algorithms, such as Recursive Least Square (RLS), Affine Projection (AP) and Kalman Filter (KF), contain two important updates per iteration cycle. Covariance Matrix Approximation (CMA) update and the Gradient Vector (GV) update. Usually, the computational effort of updating Covariance Matrix Approximation (CMA) requires greater computational effort than that of updating Gradient Vector (GV). Therefore, in circumstances where the sampled data in the regressor does not experience significant fluctuations, re-using the Covariance Matrix Approximation (CMA), calculated from the last iteration cycle for the current update can result in computational cost savings for real- time system identification. In this thesis, both iteration rate adjustment and Covariance Matrix Approximation (CMA) re-cycling are combined and applied to simultaneously identify the power converter model in a three-rail power conversion architecture. Besides, in multi-rail architectures, due to the high likelihood of the at-the-same-time need for real time system identification of more than one rail, it is necessary to prioritize each rail to guarantee rails with higher priority being identified first and avoid jam. In the thesis, a workflow, which comprises sequencing rails and allocating system identification task into selected rails, was proposed. The multi-respect workflow, featured of being dynamic, selectively pre-emptive, cost saving, is able to flexibly change ranks of each rail based on the application importance of rails and the severity of abrupt changes that rails are suffering to optimize waiting time and make-span of rails with higher priorities

Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 µW and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 µVrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd

Power Converters in Power Electronics

In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Earth Observatory Satellite system definition study. Report 3: Design cost trade-off studies and recommendations

An analysis of the design and cost tradeoff aspects of the Earth Observatory Satellite (EOS) development is presented. The design/cost factors that affect a series of mission/system level concepts are discussed. The subjects considered are as follows: (1) spacecraft subsystem cost tradeoffs, (2) ground system cost tradeoffs, and (3) program cost summary. Tables of data are provided to summarize the results of the analyses. Illustrations of the various spacecraft configurations are included