Using SPIN to Analyse the Tree Identification Phase of the IEEE 1394 High-Performance Serial Bus(FireWire)Protocol

We describe how the tree identification phase of the IEEE 1394 high-performance serial bus (FireWire) protocol is modelled in Promela and verified using SPIN. The verification of arbitrary system configurations is discussed

Libra: An Economy driven Job Scheduling System for Clusters

Clusters of computers have emerged as mainstream parallel and distributed platforms for high-performance, high-throughput and high-availability computing. To enable effective resource management on clusters, numerous cluster managements systems and schedulers have been designed. However, their focus has essentially been on maximizing CPU performance, but not on improving the value of utility delivered to the user and quality of services. This paper presents a new computational economy driven scheduling system called Libra, which has been designed to support allocation of resources based on the users? quality of service (QoS) requirements. It is intended to work as an add-on to the existing queuing and resource management system. The first version has been implemented as a plugin scheduler to the PBS (Portable Batch System) system. The scheduler offers market-based economy driven service for managing batch jobs on clusters by scheduling CPU time according to user utility as determined by their budget and deadline rather than system performance considerations. The Libra scheduler ensures that both these constraints are met within an O(n) run-time. The Libra scheduler has been simulated using the GridSim toolkit to carry out a detailed performance analysis. Results show that the deadline and budget based proportional resource allocation strategy improves the utility of the system and user satisfaction as compared to system-centric scheduling strategies.Comment: 13 page

Towards Generic Monitors for Object-Oriented Real-Time Maude Specifications

Non-Functional Properties (NFPs) are crucial in the design of software. Specification of systems is used in the very first phases of the software development process for the stakeholders to make decisions on which architecture or platform to use. These specifications may be an- alyzed using different formalisms and techniques, simulation being one of them. During a simulation, the relevant data involved in the anal- ysis of the NFPs of interest can be measured using monitors. In this work, we show how monitors can be parametrically specified so that the instrumentation of specifications to be monitored can be automatically performed. We prove that the original specification and the automati- cally obtained specification with monitors are bisimilar by construction. This means that the changes made on the original system by adding monitors do not affect its behavior. This approach allows us to have a library of possible monitors that can be safely added to analyze different properties, possibly on different objects of our systems, at will.Universidad de Málaga, Campus de Excelencia Internacional Andalucía Tech. Spanish MINECO/FEDER project TIN2014-52034-R, NSF Grant CNS 13-19109

Modelos de consistencia y protocolos de coherencia en DVSM

Los sistemas de Memoria Compartida Distribuida (DSM) son el vehículo ideal para la programación paralela debido a las facilidades de programación que brinda la memoria compartida y a la escalabilidad de los sistemas distribuidos. El reto de construir un DSM es lograr una buena performance sobre un amplio espectro de programas paralelos sin requerir que los programadores reestructuren sus programas de memoria compartida. Por su parte, en la implementación por software de estos sistemas, del tipo DVSM, se tiene la tendencia a una gran cantidad de comunicación que se debe realizar entre procesadores para mantener consistente la memoria. Desde la creación de los primeros DVSM se han aplicado diversas alternativas para aliviar este cuello de botella en la performance. La mayoría de ellas se concentran en los modelos de consistencia de memoria, i.e. se encargan de definir como se ve la memoria compartida frente al programador, determinan la interface entre el programador y el sistema [11]. Una tendencia en estas alternativas es el empleo de modelos relajados, los cuales aumentan la complejidad del protocolo pero reducen el tráfico en la red mientras siguen manteniendo consistente la memoria. Ejemplo de ello es la lazy release consistency (LRC) [1] en TreadMarks [7] o la scope consistency (ScC) [2] en JIAJIA v1.1 [5]. Otras implementaciones tratan de reducir el tráfico refinando protocolos de coherencia de memoria, como el protocolo de migración de home en JIAJIA v2.1 [8] y el de home migratorio en JUMP [4].Eje: Redes, Arquitectura, Sistemas Distribuidos y Tiempo RealRed de Universidades con Carreras en Informática (RedUNCI

Assessment of Response Time for New Multi Level Feedback Queue Scheduler

Response time is one of the characteristics of scheduler, happens to be a prominent attribute of any CPU scheduling algorithm. The proposed New Multi Level Feedback Queue [NMLFQ] Scheduler is compared with dynamic, real time, Dependent Activity Scheduling Algorithm (DASA) and Lockes Best Effort Scheduling Algorithm (LBESA). We abbreviated beneficial result of NMLFQ scheduler in comparison with dynamic best effort schedulers with respect to response time.Comment: 7 pages, 5 figure

Modelos de consistencia y protocolos de coherencia en DVSM

Los sistemas de Memoria Compartida Distribuida (DSM) son el vehículo ideal para la programación paralela debido a las facilidades de programación que brinda la memoria compartida y a la escalabilidad de los sistemas distribuidos. El reto de construir un DSM es lograr una buena performance sobre un amplio espectro de programas paralelos sin requerir que los programadores reestructuren sus programas de memoria compartida. Por su parte, en la implementación por software de estos sistemas, del tipo DVSM, se tiene la tendencia a una gran cantidad de comunicación que se debe realizar entre procesadores para mantener consistente la memoria. Desde la creación de los primeros DVSM se han aplicado diversas alternativas para aliviar este cuello de botella en la performance. La mayoría de ellas se concentran en los modelos de consistencia de memoria, i.e. se encargan de definir como se ve la memoria compartida frente al programador, determinan la interface entre el programador y el sistema [11]. Una tendencia en estas alternativas es el empleo de modelos relajados, los cuales aumentan la complejidad del protocolo pero reducen el tráfico en la red mientras siguen manteniendo consistente la memoria. Ejemplo de ello es la lazy release consistency (LRC) [1] en TreadMarks [7] o la scope consistency (ScC) [2] en JIAJIA v1.1 [5]. Otras implementaciones tratan de reducir el tráfico refinando protocolos de coherencia de memoria, como el protocolo de migración de home en JIAJIA v2.1 [8] y el de home migratorio en JUMP [4].Eje: Redes, Arquitectura, Sistemas Distribuidos y Tiempo RealRed de Universidades con Carreras en Informática (RedUNCI

Loop detection and prevention mechanism in multiprotocol label switching

The extended color thread algorithm is based on running a thread hop by hop before the labels are distributed inside a MPLS Cloud Since the path for the data packets is set beforehand, the loop formation occurs at the control path. The shortest paths between selected source and destination have been calculated using Dijkstra\u27s shortest path algorithm and threads are allowed to extend through the routers. With the passage of each next hop, a distributed procedure is executed within the thread, generating a unique color at nodes. This keeps a track on router\u27s control path and at the same time ensures that no loop formation occurs. In loop prevention mode, a router transmits a label mapping, when it rewinds the thread for that particular LSP. Likewise, if a router operates in loop detection mode, it returns a label-mapping message without a thread object, after receiving a colored thread. The scheme is a loop prevention scheme, thus, ensuring loop detection and loop mitigation. The same algorithm is then extended to a proposed MPLS environment with global label space. (Abstract shortened by UMI.)

Технологія віртуалізації. Динамічна реконфігурація ресурсів обчислювального кластера

На основании выполненного анализа современных платформ аппаратно-программной виртуализации обоснована целесообразность использования и исследования виртуальных машин на платформе Microsoft Hyper-V R2 в качестве узлов вычислительного кластера. Концепция создания гибких гомогенных архитектур кластерных систем углублена за счет возможности формирования динамически реконфигурируемой кластерной вычислительной системы с использованием механизмов виртуализации платформы Microsoft Hyper-V. Показана актуальность использования аппаратной платформы персональных компьютеров и серверов для реконфигурации ресурсов вычислительных кластеров.На основі виконаного аналізу сучасних платформ апаратно-програмної віртуалізації обґрунтовано доцільність використання і дослідження віртуальних машин на платформі Microsoft Hyper-V R2 як вузлів обчислювального кластера. Концепцію створення гнучких гомогенних архітектур кластерних систем поглиблено за рахунок можливості формування динамічно реконфігурованої кластерної обчислювальної системи з використанням механізмів віртуалізації платформи Microsoft Hyper-V. Показано актуальність використання апаратної платформи персональних комп’ютерів і серверів для реконфігурації ресурсів обчислювальних кластерів.On the basis of performed analysis of modern hardware and software virtualization platforms it is proved the practicability of usage and researching of virtual machines on the Microsoft Hyper-V R2 platform as a compute cluster nodes. The concept of flexible homogeneous cluster architectures construction was expanded with ability of dynamically reconfigurable cluster computing system implementation using Microsoft Hyper-V technology virtualization features. The urgency of hardware platform of personal computers and servers for reconfiguration of the resources of computing clusters is shown