A Horizontally Reconfigurable Architecture for Extended Precision Arithmetic (Parallel Computing, Condition Codes Factoring).

A special computer for high-precision arithmetic and parallel processing which features an ALU that is dynamically reconfigurable under program control has been designed and a prototype machine constructed. The 256-bit ALU consists of eight 32-bit slices each of which has its own ALU operation code in each microinstruction. The slices can remain logically separated from each other, or can be dynamically connected to either or both of their neighbors under control of a segment control code that is part of each microinstruction. The result is a unique parallel architecture which provides real parallelism to user programs at the instruction level while globally retaining a sequential control structure. Management of parallelism is achieved through a two level hierarchy of condition codes and extended instruction sets to support conditional instruction execution. New types of parallel micro-programming tools introduce a system for reconfiguration management and parallel programming. An assembler, debug simulator, and interactive operating environment have been implemented. An analysis of the instruction times to execute arithmetic operations on the machine show that it will be exceptionally fast for problems in computational number theory and factoring of integers

The RDT network Router Chip

Design Outline The RDT network Router chip is a versatile router for the massively parallel computer prototype JUMP-1, which is currently under development by collaboration between 7 Japanese universities The major goal of this project is to establish techniques for building an ecient distributed shared memory on a massively parallel processor. For this purpose, the reduced hierarchical bit-map directory (RHBD) schemes In order to implement (RHBD) schemes eciently, we proposed a novel interconnection network RDT (Recursive Diagonal Torus) By using the 0.5BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock(60MHz). Long coaxial cables(4m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buers allow to push and pull a it of the packet simultaneously. The mixed design approach with schematic and VHDL permits the development of the complicated chip with 90,522 gates in a year. 2 JUMP-1 and the RDT JUMP-1[1] consists of clusters connected with an interconnection network RDT 2.1 Interconnection network RD

Processor-In-Memory (PIM) Based Architectures for PetaFlops Potential Massively Parallel Processing

The report summarizes the work performed at the University of Notre Dame under a NASA grant from July 15, 1995 through July 14, 1996. Researchers involved in the work included the PI, Dr. Peter M. Kogge, and three graduate students under his direction in the Computer Science and Engineering Department: Stephen Dartt, Costin Iancu, and Lakshmi Narayanaswany. The organization of this report is as follows. Section 2 is a summary of the problem addressed by this work. Section 3 is a summary of the project's objectives and approach. Section 4 summarizes PIM technology briefly. Section 5 overviews the main results of the work. Section 6 then discusses the importance of the results and future directions. Also attached to this report are copies of several technical reports and publications whose contents directly reflect results developed during this study

Wind energy harvester interface for sensor nodes

The research topic is developping a power converting interface for the novel FLEHAP wind energy harvester allowing the produced energy to be used for powering small wireless nodes. The harvester\u2019s electrical characteristics were studied and a strategy was developped to control and mainting a maximum power transfer. The electronic power converter interface was designed, containing an AC/DC Buck-Boost converter and controlled with a low power microcontroller. Different prototypes were developped that evolved by reducing the sources of power loss and rendering the system more efficient. The validation of the system was done through simulations in the COSMIC/DITEN lab using generated signals, and then follow-up experiments were conducted with a controllable wind tunnel in the DIFI department University of Genoa. The experiment results proved the functionality of the control algorithm as well as the efficiency that was ramped up by the hardware solutions that were implemented, and generally met the requirement to provide a power source for low-power sensor nodes

Probabilistic structural mechanics research for parallel processing computers

Aerospace structures and spacecraft are a complex assemblage of structural components that are subjected to a variety of complex, cyclic, and transient loading conditions. Significant modeling uncertainties are present in these structures, in addition to the inherent randomness of material properties and loads. To properly account for these uncertainties in evaluating and assessing the reliability of these components and structures, probabilistic structural mechanics (PSM) procedures must be used. Much research has focused on basic theory development and the development of approximate analytic solution methods in random vibrations and structural reliability. Practical application of PSM methods was hampered by their computationally intense nature. Solution of PSM problems requires repeated analyses of structures that are often large, and exhibit nonlinear and/or dynamic response behavior. These methods are all inherently parallel and ideally suited to implementation on parallel processing computers. New hardware architectures and innovative control software and solution methodologies are needed to make solution of large scale PSM problems practical

Bidirectional Electric Vehicles Service Integration in Smart Power Grid with Renewable Energy Resources

As electric vehicles (EVs) become more popular, the utility companies are forced to increase power generations in the grid. However, these EVs are capable of providing power to the grid to deliver different grid ancillary services in a concept known as vehicle-to-grid (V2G) and grid-to-vehicle (G2V), in which the EV can serve as a load or source at the same time. These services can provide more benefits when they are integrated with Photovoltaic (PV) generation. The proper modeling, design and control for the power conversion systems that provide the optimum integration among the EVs, PV generations and grid are investigated in this thesis. The coupling between the PV generation and integration bus is accomplished through a unidirectional converter. Precise dynamic and small-signal models for the grid-connected PV power system are developed and utilized to predict the system’s performance during the different operating conditions. An advanced intelligent maximum power point tracker based on fuzzy logic control is developed and designed using a mix between the analytical model and genetic algorithm optimization. The EV is connected to the integration bus through a bidirectional inductive wireless power transfer system (BIWPTS), which allows the EV to be charged and discharged wirelessly during the long-term parking, transient stops and movement. Accurate analytical and physics-based models for the BIWPTS are developed and utilized to forecast its performance, and novel practical limitations for the active and reactive power-flow during G2V and V2G operations are stated. A comparative and assessment analysis for the different compensation topologies in the symmetrical BIWPTS was performed based on analytical, simulation and experimental data. Also, a magnetic design optimization for the double-D power pad based on finite-element analysis is achieved. The nonlinearities in the BIWPTS due to the magnetic material and the high-frequency components are investigated rely on a physics-based co-simulation platform. Also, a novel two-layer predictive power-flow controller that manages the bidirectional power-flow between the EV and grid is developed, implemented and tested. In addition, the feasibility of deploying the quasi-dynamic wireless power transfer technology on the road to charge the EV during the transient stops at the traffic signals is proven