Comparison between Two Algorithms of 32kb/s ADPCM using QAM Signal at 16.8kb/s

This paper studies the  comparison between two algorithms of 32kb/s ADPCM systems. The first algorithm uses 4-bit quantizer with sampling rate of 8000 sample/sec, and the second algorithm uses 5-bit quantizer with sampling rate of 6400 sample/sec. The comparison is done using QAM signal at data rate of 16.8kb/s. Two models of QAM signals are used, the first model operates at symbol rate of 2400 baud   with each symbol is represented by 7-bit, while, the second model operates at symbol rate of 2800 baud with each symbol is represented by 6-bit. The contribution of this paper is that sending the second model of QAM signal over ADPCM with 5-bit quantizer. Simulation results show that the performance of ADPCM with 5-bit quantizer is better than 4-bit quantizer for both models of QAM signals. Also, the performance of ADPCM using second model is better than the first model. Furthermore, the performance with circular constellation is better than rectangular on

Performance and area evaluations of processor-based benchmarks on FPGA devices

The computing system on SoCs is being long-term research since the FPGA technology has emerged due to its personality of re-programmable fabric, reconfigurable computing, and fast development time to market. During the last decade, uni-processor in a SoC is no longer to deal with the high growing market for complex applications such as Mobile Phones audio and video encoding, image and network processing. Due to the number of transistors on a silicon wafer is increasing, the recent FPGAs or embedded systems are advancing toward multi-processor-based design to meet tremendous performance and benefit this kind of systems are possible. Therefore, is an upcoming age of the MPSoC. In addition, most of the embedded processors are soft-cores, because they are flexible and reconfigurable for specific software functions and easy to build homogenous multi-processor systems for parallel programming. Moreover, behavioural synthesis tools are becoming a lot more powerful and enable to create datapath of logic units from high-level algorithms such as C to HDL and available for partitioning a HW/SW concurrent methodology. A range of embedded processors is able to implement on a FPGA-based prototyping to integrate the CPUs on a programmable device. This research is, firstly represent different types of computer architectures in modern embedded processors that are followed in different type of software applications (eg. Multi-threading Operations or Complex Functions) on FPGA-based SoCs; and secondly investigate their capability by executing a wide-range of multimedia software codes (Integer-algometric only) in different models of the processor-systems (uni-processor or multi-processor or Co-design), and finally compare those results in terms of the benchmarks and resource utilizations within FPGAs. All the examined programs were written in standard C and executed in a variety numbers of soft-core processors or hardware units to obtain the execution times. However, the number of processors and their customizable configuration or hardware datapath being generated are limited by a target FPGA resource, and designers need to understand the FPGA-based tradeoffs that have been considered - Speed versus Area. For this experimental purpose, I defined benchmarks into DLP / HLS catalogues, which are "data" and "function" intensive respectively. The programs of DLP will be executed in LEON3 MP and LE1 CMP multi-processor systems and the programs of HLS in the LegUp Co-design system on target FPGAs. In preliminary, the performance of the soft-core processors will be examined by executing all the benchmarks. The whole story of this thesis work centres on the issue of the execute times or the speed-up and area breakdown on FPGA devices in terms of different programs

A Hybrid voice/text electronic mail system: an application of the integrated services digital network

The objective of this thesis is to present a useful application for the Integrated Services Digital Network (ISDN) that is expected to one day replace the analog phone system in use today. ISDN itself and its continuing evolution are detailed. The system developed as a part of this thesis involved the creation of an inexpensive phone terminal that can serve as an ISDN terminal and also as a bridge to a Local Area Network (LAN). The phone terminal provides a hybrid electronic mail system that allows the attachment of speech to text within a message. Messages created with this phone terminal could theoretically be sent locally using the LAN interface and globally using ISDN to other users with either phone terminals or multimedia personal computers. For this project, the two phone terminals created were interconnected via an Ethernet and using an 80486 PC to act as a Central Office System. This Central Office System provides speech/message storage for the phone terminals. It makes use of speech compression techniques to minimize the storage requirements. The speech compression techniques used as well as the field of speech coding in general are discussed

Un système interactif pour le prototypage virtuel coopératif

We present in this thesis the study and implementation of an interactive system for cooperative prototyping of virtual models. These works make use of several technologies from different scientific backgrounds; Virtual Reality is at the crossroads of many disciplines. Our goal is not to replace right now a CAD system with a system such as that we propose in this thesis. Indeed, the power of the machines does not allow yet the management of virtual objects with an accuracy comparable to that of CAD tools. While our system is intuitive and interactive but does not have enough machine power to compete with such precision tools; This precision is however necessary for the industry. This development will be achieved, for sure, but it is more reasonable for the moment to see virtual reality as a complement to CAD.Nous présentons dans ce mémoire l’étude et la réalisation d’un système interactif pour le prototypage coopératif de maquettes virtuelles. Ces travaux font usage de plusieurs technologies issues de milieux scientifiques variés ; la réalité virtuelle n’est elle pas à la croisée des chemins de nombreuses disciplines ? Notre objectif n’est pas de remplacer dès à présent un système de CAO par un système tel que celui que nous proposons dans ce mémoire. En effet, la puissance des machines ne permet pas encore la gestion d’objets virtuels avec une précision comparable à celle des outils de CAO. Certes notre système est intuitif et interactif mais il ne dispose pas d’assez de puissance machine pour rivaliser en précision avec de tels outils ; cette précision est pourtant nécessaire pour l’industrie. Cette évolution se fera, c’est sûr, mais il est pour l’instant plus raisonnable de voir la réalité virtuelle comme un complément de la CAO

A comparison of adaptive predictors in sub-band coding

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1987.Bibliography: leaves 82-85.by Paul Ning.M.S

Distributed multimedia systems

A distributed multimedia system (DMS) is an integrated communication, computing, and information system that enables the processing, management, delivery, and presentation of synchronized multimedia information with quality-of-service guarantees. Multimedia information may include discrete media data, such as text, data, and images, and continuous media data, such as video and audio. Such a system enhances human communications by exploiting both visual and aural senses and provides the ultimate flexibility in work and entertainment, allowing one to collaborate with remote participants, view movies on demand, access on-line digital libraries from the desktop, and so forth. In this paper, we present a technical survey of a DMS. We give an overview of distributed multimedia systems, examine the fundamental concept of digital media, identify the applications, and survey the important enabling technologies.published_or_final_versio

Performance evaluation of currently available VLSI implementations satisfying U-interface requirements for an ISDN in South Africa.

A project report submitted to the Faculty of Engineering, University of the Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the degree of Master of Science in Engineering.This project report examines the performance of three VLSI U-interface implementations satisfying the requirements of Basic Access on an ISDN. The systems evaluated are the Intel 89120,Siemens PEB2090 and STC DSP144, operating on 2BIQ, MMS4J and SU32 line codes respectively. Before evaluating the three abovementioned systems, a review of the underlying principles of U-interface technology is presented. Included in the review are aspects of transmission line theory, line coding, echo-cancellation, decision feedback equalisation, and pulse density modulation. The functional specifications of the three systems are then presented followed by a practical evaluation of each system. As an aid to testing the transmission systems, an evaluation board has been designed and built. The latter provides the necessary functionality to correctly activate each system, as well as the appropriate interfacing requirements for the error-rate tester. The U-interface transmission systems are evaluated on a number of test-loops, comprising sections of cable varying in length and gauge. Additionally, impairments are injected into data-carrying cables, in order to test the performance of each system in the presence of noise. The results of each test are recorded and analysed. Finally, a recommendation is made in favour of the 2BIQ U-interface. It is shown to offer superior transmission performance, at the expense of a slightly higher transmit-power level.Andrew Chakane 201

Media gateway utilizando um GPU

Mestrado em Engenharia de Computadores e Telemátic