A high-speed, folding, analog-to-digital converter

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 99-100).by Paul Louis.M.S

700mV low power low noise implantable neural recording system design

This dissertation presents the work for design and implementation of a low power, low noise neural recording system consisting of Bandpass Amplifier and Pipelined Analog to Digital Converter (ADC) for recording neural signal activities. A low power, low noise two stage neural amplifier for use in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is utilized to amplify the neural signals. The optimization of the number of amplifier stages is discussed to achieve the minimum power and area consumption. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7 μVrms and 1.90 μW respectively. The measured result shows that the optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording. The advantage of power consumption of Pipelined ADC over Successive Approximation Register (SAR) ADC and Delta-Sigma ADC is discussed. An 8 bit fully differential (FD) Pipeline ADC for use in a smart RFID is presented in this dissertation. The Multiplying Digital to Analog Converter (MDAC) utilizes a novel offset cancellation technique robust to device leakage to reduce the input drift voltage. Simulation results of static and dynamic performance show this low power Pipeline ADC is suitable for multi-channel neural recording applications. The performance of all proposed building blocks is verified through test chips fabricated in IBM 180nm CMOS process. Both bench-top and real animal test results demonstrate the system's capability of recording neural signals for neural spike detection

Design considerations for a monolithic, GaAs, dual-mode, QPSK/QASK, high-throughput rate transceiver

A monolithic, GaAs, dual mode, quadrature amplitude shift keying and quadrature phase shift keying transceiver with one and two billion bits per second data rate is being considered to achieve a low power, small and ultra high speed communication system for satellite as well as terrestrial purposes. Recent GaAs integrated circuit achievements are surveyed and their constituent device types are evaluated. Design considerations, on an elemental level, of the entire modem are further included for monolithic realization with practical fabrication techniques. Numerous device types, with practical monolithic compatability, are used in the design of functional blocks with sufficient performances for realization of the transceiver

Investigation of Various Shaping Methods for the Development of a Fully-Monolithic CMOS Constant-Fraction Discriminator

In this work the design of a constant-fraction discriminator (CFD) fabricated in the Orbit Semiconductor l.2-Jl n-well CMOS process is presented. This timing pick-off circuit is designed for use in the readout electronics of the Lead-Scintillator subsystem of the Pioneering High Eenergy Nuclear Ion eXperiment (PHENIX) Electromagnetic Calorimeter at the Relativistic Heavy Ion Collider (RHIC). The design was driven by stringent requirements including low power consumption, small area, arrayable, low cost and a fully integratable shaping network. Various integratable CFD shaping methods are investigated, and the candidate methods chosen for fabrication were the distributed R-C delay-line shaping, lumped-element R-C shaping and Nowlin method shaping. An additional channel of ideal delay-line shaping, utilizing coaxial cable to generate delay, was fabricated and used for a reference in comparing methods. These shaping methods are compared on the basis of die area, time walk performance and timing jitter performance as implemented using the CMOS CFD presented. Each shaping method investigated required no power from the dc supply. Die area for the distributed R-C delay-line, lumped-element R-C, Nowlin method and ideal delay-line (fraction circuit only) were 172 Jl X 70 Jl, 160 Jl X 65 Jl, 179 Jl X 53 Jl and 67 Jl X65Jl,respectively. Timewalkovera100:1dynamicrange(-2Vpeakto-20mVpeak) for these shaping methods in turn was found to be ± 175 ps, ± 150ps , ± 150 ps and ± 185 ps, respectively. Timing jitter performance with a minimum input signal (-20 mVpeak) in rms units for the four methods in turn were 65 ps, 85 ps, 100 ps and 65 ps. The average power dissipated per CFD channel was found to be approximately 12 mW

A low-noise, wide-band CMOS charge-sensitive preamplifier for use with a cadmium zinc telluride strip detector in a high-resolution small animal x-ray CT system

A low-noise, wide-band CMOS charge-sensitive preamplifier has been designed for use with a Cadmium Zinc Telluride (CZT) strip detector in the Oak Ridge NationalLaboratory\u27s (ORNL) MicroCAT small animal x-ray CT imaging system. The Characteristics of the CZT strip detector have been studied to optimize the design of the preamplifier, and are presented herein. The design of the charge-sensitive preamplifier(CSP) is discussed in detail, and test results are presented and discussed. The CSP was found to have a 10 - 90 % rise time of 23 ns, a charge gain of √ Hz x 1012 V/C, a dynamic range of + 0.9 V and - 2 V, and an equivalent input noise of 13 .nV√Hz 1 kHz and 2.2 nV 1 MHz. The CSP coupled to an Ortec 571 shaping amplifier has an Equivalent Noise Charge (ENC) minimum of 400 rms electrons for unipolar shaping at peaking time of 14 µs with a 4 pF detector capacitance. The system, with the same configuration, hasan ENC minimum of 550 rms electrons for bipolar shaping at the zero crossover of 15 µs.The prototype preamplifier has been fabricated in the AMI 1.2 µm process through the MOSIS microelectronics prototyping program

Proposal for an 8-bit Radiation Hardened Flash A/d Converter

Electrical Engineerin

Dynamic input match correction in R.F. low noise amplifiers

An R.F. circuit that recognizes its faults, and then corrects its performance in real-time has been the holy-grail of RFIC design. This work presents, for the first time, a complete architecture and successful implementation of such a circuit. It is the first step towards the grand vision of fault-free, package independent, integrated R.F. Front End circuitry. The performance of R.F. front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input. These inductances have wide tolerances and are difficult to co-design for. A novel methodology, which overcomes current obstacles plaguing such an objective, is proposed wherein the affected performance metric of the circuit is quantified, and the appropriate design parameter is modified in real-time, thus enabling self-correction. This proof of concept is demonstrated by designing a cascode LNA and the complete self-correction circuit in IBM 0.25 µm CMOS RF process. The self-correction circuitry ascertains the input match frequency of the circuit by measuring its performance and determines the frequency interval by which it needs to be shifted to restore it to the desired value. It then feeds back a digital word to the LNA which adaptively corrects its input-match. It offers the additional flexibility of using different packages for the front-end since it renders the circuitry independent of package parasitics, by re-calibrating the input match on-the-fly. The circuitry presented in this work offers the advantages of low power, robustness, absence of DSP cores or processors, reduction in design cycle times, guaranteed optimal performance under varying conditions and fast correction times (less than 30 µs)

Analog, hybrid, and digital simulation

Analog, hybrid, and digital computerized simulation technique

High performance amplifier topologies implemented with a micro-machined vibrating capacitor

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (leaves 201-206).In this work, the design of a MEMS based differential amplifier is investigated. The goal of this investigation is to design, fabricate and characterize a differential amplifier whose performance is based on a physically coupled, but electrically isolated fully differential mechanical transconductor input stage that is fabricated using SOI-MEMS technology. The MEMS sensor will act as a vibrating capacitor input stage. It will provide galvanic isolation and up-modulation of the input signal as it vibrates. The galvanic isolation facilitates low-leakage inputs and a very wide input common mode voltage range. The up-modulation provides a means for achieving a low input referred offset voltage and low-noise via the use of correlated double sampling or chopper stabilization. At the system level, this amplifier consists of two major loops: the drive loop and a sense loop. The drive loop includes half of the MEMS structure along with some electronics and provides a means of moving the beam at a constant frequency. The drive loop's design was facilitated by describing function analysis. The drive loop vibrated the beam at its mechanical resonance because at that frequency, the displacement of the beam is maximized for a given electrostatic force and consequently, the sensitivity of the amplifier is maximized. The sense loop includes the other half of the beam and some electronics whose role is to process the differential input signal applied at the MEMS structure's inputs. Common-mode rejection is performed by the mechanical transconductor, while the sense loop's crossover frequency sets the signal bandwidth.(cont.) The performance of the amplifier agreed very well with hand calculations and simulations. The noise performance was dominated by the total noise at the preamplifier's input. The noise performance achieved in this design was 55 ... Hz , which is higher than that of other high performance amplifiers. Based on the analytical model created for the amplifier, a noise level of 450 ... Hz can be achieved when the circuitry is fully integrated with the sensor.by Akin Adeniyi Aina.Ph.D