Model-based symbolic design space exploration at the electronic system level: a systematic approach

In this thesis, a novel, fully systematic approach is proposed that addresses the automated design space exploration at the electronic system level. The problem is formulated as multi-objective optimization problem and is encoded symbolically using Answer Set Programming (ASP). Several specialized solvers are tightly coupled as background theories with the foreground ASP solver under the ASP modulo Theories (ASPmT) paradigm. By utilizing the ASPmT paradigm, the search is executed entirely systematically and the disparate synthesis steps can be coupled to explore the search space effectively.In dieser Arbeit wird ein vollständig systematischer Ansatz präsentiert, der sich mit der Entwurfsraumexploration auf der elektronischen Systemebene befasst. Das Problem wird als multikriterielles Optimierungsproblem formuliert und symbolisch mit Hilfe von Answer Set Programming (ASP) kodiert. Spezialisierte Solver sind im Rahmen des ASP modulo Theories (ASPmT) Paradigmas als Hintergrundtheorien eng mit dem ASP Solver gekoppelt. Durch die Verwendung von ASPmT wird die Suche systematisch ausgeführt und die individuellen Schritte können gekoppelt werden, um den Suchraum effektiv zu durchsuchen

Optimization Algorithms For The Multiple Constant Multiplications Problem

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu tezde, birden fazla katsayının çarpımı (MCM) problemi, bir başka deyişle, bir değişkenin birden fazla katsayı ile çarpımının minimum sayıda toplama/çıkarma işlemi kullanılarak gerçeklenmesi için tasarlanmış kesin ve yaklaşık algoritmalar sunulmaktadır. Bir kesin alt ifade eliminasyonu (CSE) algoritmasının tasarımında, MCM problemini bir 0-1 tamsayı lineer programlama problemi olarak modelleyen daha önceden önerilmiş bir algoritma temel alınmıştır. Kesin CSE algoritması içinde, alan ve gecikme ölçütlerini ele alabilmek için yeni bir kesin model önerilmektedir. Kesin CSE algoritması tarafından taranacak arama uzayını küçültmek için problem indirgeme ve model basitleştirme teknikleri sunulmaktadır. Bu tekniklerin kullanımının kesin CSE algoritmasının daha büyük örnekler üzerinde uygulanmasına olanak sağladığı gösterilmektedir. Ayrıca, bu teknikler ile donatılmış kesin CSE algoritması, katsayıları genel sayı gösteriminde ele alacak ve kesin CSE algoritmasından daha iyi sonuçlar elde edecek şekilde genişletilmektedir. Bunların yanında, gerçek boyutlu örnekler üzerinde uygulanabilen bir kesin graf tabanlı algoritma sunulmaktadır. Bu kesin algoritmalara ek olarak, minimum sonuçlara oldukça yakın çözümler bulabilen ve kesin algoritmaların ele almakta zorlandığı örneklere uygulanabilen yaklaşık CSE ve graf tabanlı algoritmalar verilmektedir. Bu tezde önerilen kesin ve yaklaşık algoritmaların daha önceden önerilmiş sezgisel yöntemlerden daha iyi sonuçlar verdiği gösterilmektedir. Bunların yanısıra, bu tezde, kesin CSE algoritması gecikme kısıtı altında alanın minimize edilmesi, kapı seviyesinde alanın minimize edilmesi ve yüksek hızlı sayısal sonlu impuls cevaplı filtrelerin tasarımında alanın optimize edilmesi problemlerine uygulanmaktadır.In this thesis, exact and approximate algorithms designed for the multiple constant multiplications (MCM) problem, i.e., the implementation of the multiplication of a variable with multiple constants using minimum number of addition/subtraction operations, are introduced. In the design of an exact common subexpression elimination (CSE) algorithm, we relied on the previously proposed algorithm that models the MCM problem as a 0-1 integer linear programming problem. To handle the area and delay parameters in the exact CSE algorithm, a new exact model is proposed. To reduce the search space to be explored by the exact algorithm, problem reduction and model simplification techniques are introduced. It is shown that the use of these techniques enable the exact CSE algorithm to be applied on larger size instances. Also, the exact CSE algorithm equipped with these techniques is extended to handle the constants under general number representation yielding better solutions than those of the exact CSE algorithm. Besides, an exact graph-based algorithm that can be applied on real size instances is introduced. In addition to the exact algorithms, approximate CSE and graph-based algorithms that find similar results with the minimum solutions and can be applied on instances that the exact algorithms cannot deal with are presented. It is shown that the exact and approximate algorithms proposed in this thesis give better solutions than those of the previously proposed heuristic algorithms. Furthermore, in this thesis, the exact CSE algorithm is applied on the minimization of area under a delay constraint, the minimization of area at gate-level, and the optimization of area in high-speed digital finite impulse response filters synthesis problems.DoktoraPh

Methoden und Beschreibungssprachen zur Modellierung und Verifikation vonSchaltungen und Systemen: MBMV 2015 - Tagungsband, Chemnitz, 03. - 04. März 2015

Der Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) findet nun schon zum 18. mal statt. Ausrichter sind in diesem Jahr die Professur Schaltkreis- und Systementwurf der Technischen Universität Chemnitz und das Steinbeis-Forschungszentrum Systementwurf und Test. Der Workshop hat es sich zum Ziel gesetzt, neueste Trends, Ergebnisse und aktuelle Probleme auf dem Gebiet der Methoden zur Modellierung und Verifikation sowie der Beschreibungssprachen digitaler, analoger und Mixed-Signal-Schaltungen zu diskutieren. Er soll somit ein Forum zum Ideenaustausch sein. Weiterhin bietet der Workshop eine Plattform für den Austausch zwischen Forschung und Industrie sowie zur Pflege bestehender und zur Knüpfung neuer Kontakte. Jungen Wissenschaftlern erlaubt er, ihre Ideen und Ansätze einem breiten Publikum aus Wissenschaft und Wirtschaft zu präsentieren und im Rahmen der Veranstaltung auch fundiert zu diskutieren. Sein langjähriges Bestehen hat ihn zu einer festen Größe in vielen Veranstaltungskalendern gemacht. Traditionell sind auch die Treffen der ITGFachgruppen an den Workshop angegliedert. In diesem Jahr nutzen zwei im Rahmen der InnoProfile-Transfer-Initiative durch das Bundesministerium für Bildung und Forschung geförderte Projekte den Workshop, um in zwei eigenen Tracks ihre Forschungsergebnisse einem breiten Publikum zu präsentieren. Vertreter der Projekte Generische Plattform für Systemzuverlässigkeit und Verifikation (GPZV) und GINKO - Generische Infrastruktur zur nahtlosen energetischen Kopplung von Elektrofahrzeugen stellen Teile ihrer gegenwärtigen Arbeiten vor. Dies bereichert denWorkshop durch zusätzliche Themenschwerpunkte und bietet eine wertvolle Ergänzung zu den Beiträgen der Autoren. [... aus dem Vorwort

Practical Techniques for Improving Performance and Evaluating Security on Circuit Designs

As the modern semiconductor technology approaches to nanometer era, integrated circuits (ICs) are facing more and more challenges in meeting performance demand and security. With the expansion of markets in mobile and consumer electronics, the increasing demands require much faster delivery of reliable and secure IC products. In order to improve the performance and evaluate the security of emerging circuits, we present three practical techniques on approximate computing, split manufacturing and analog layout automation. Approximate computing is a promising approach for low-power IC design. Although a few accuracy-configurable adder (ACA) designs have been developed in the past, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. We investigate a simple ACA design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. The simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% less area. One variant of this design provides finer-grained and larger tunability than that of the previous works. Moreover, we propose a delay-adaptive self-configuration technique to further improve the accuracy-delay-power tradeoff. Split manufacturing prevents attacks from an untrusted foundry. The untrusted foundry has front-end-of-line (FEOL) layout and the original circuit netlist and attempts to identify critical components on the layout for Trojan insertion. Although defense methods for this scenario have been developed, the corresponding attack technique is not well explored. Hence, the defense methods are mostly evaluated with the k-security metric without actual attacks. We develop a new attack technique based on structural pattern matching. Experimental comparison with existing attack shows that the new attack technique achieves about the same success rate with much faster speed for cases without the k-security defense, and has a much better success rate at the same runtime for cases with the k-security defense. The results offer an alternative and practical interpretation for k-security in split manufacturing. Analog layout automation is still far behind its digital counterpart. We develop the layout automation framework for analog/mixed-signal ICs. A hierarchical layout synthesis flow which works in bottom-up manner is presented. To ensure the qualified layouts for better circuit performance, we use the constraint-driven placement and routing methodology which employs the expert knowledge via design constraints. The constraint-driven placement uses simulated annealing process to find the optimal solution. The packing represented by sequence pairs and constraint graphs can simultaneously handle different kinds of placement constraints. The constraint-driven routing consists of two stages, integer linear programming (ILP) based global routing and sequential detailed routing. The experiment results demonstrate that our flow can handle complicated hierarchical designs with multiple design constraints. Furthermore, the placement performance can be further improved by using mixed-size block placement which works on large blocks in priority

Doctor of Philosophy

dissertationThe embedded system space is characterized by a rapid evolution in the complexity and functionality of applications. In addition, the short time-to-market nature of the business motivates the use of programmable devices capable of meeting the conflicting constraints of low-energy, high-performance, and short design times. The keys to achieving these conflicting constraints are specialization and maximally extracting available application parallelism. General purpose processors are flexible but are either too power hungry or lack the necessary performance. Application-specific integrated circuits (ASICS) efficiently meet the performance and power needs but are inflexible. Programmable domain-specific architectures (DSAs) are an attractive middle ground, but their design requires significant time, resources, and expertise in a variety of specialties, which range from application algorithms to architecture and ultimately, circuit design. This dissertation presents CoGenE, a design framework that automates the design of energy-performance-optimal DSAs for embedded systems. For a given application domain and a user-chosen initial architectural specification, CoGenE consists of a a Compiler to generate execution binary, a simulator Generator to collect performance/energy statistics, and an Explorer that modifies the current architecture to improve energy-performance-area characteristics. The above process repeats automatically until the user-specified constraints are achieved. This removes or alleviates the time needed to understand the application, manually design the DSA, and generate object code for the DSA. Thus, CoGenE is a new design methodology that represents a significant improvement in performance, energy dissipation, design time, and resources. This dissertation employs the face recognition domain to showcase a flexible architectural design methodology that creates "ASIC-like" DSAs. The DSAs are instruction set architecture (ISA)-independent and achieve good energy-performance characteristics by coscheduling the often conflicting constraints of data access, data movement, and computation through a flexible interconnect. This represents a significant increase in programming complexity and code generation time. To address this problem, the CoGenE compiler employs integer linear programming (ILP)-based 'interconnect-aware' scheduling techniques for automatic code generation. The CoGenE explorer employs an iterative technique to search the complete design space and select a set of energy-performance-optimal candidates. When compared to manual designs, results demonstrate that CoGenE produces superior designs for three application domains: face recognition, speech recognition and wireless telephony. While CoGenE is well suited to applications that exhibit a streaming behavior, multithreaded applications like ray tracing present a different but important challenge. To demonstrate its generality, CoGenE is evaluated in designing a novel multicore N-wide SIMD architecture, known as StreamRay, for the ray tracing domain. CoGenE is used to synthesize the SIMD execution cores, the compiler that generates the application binary, and the interconnection subsystem. Further, separating address and data computations in space reduces data movement and contention for resources, thereby significantly improving performance compared to existing ray tracing approaches

A Survey of Symbolic Execution Techniques

Many security and software testing applications require checking whether certain properties of a program hold for any possible usage scenario. For instance, a tool for identifying software vulnerabilities may need to rule out the existence of any backdoor to bypass a program's authentication. One approach would be to test the program using different, possibly random inputs. As the backdoor may only be hit for very specific program workloads, automated exploration of the space of possible inputs is of the essence. Symbolic execution provides an elegant solution to the problem, by systematically exploring many possible execution paths at the same time without necessarily requiring concrete inputs. Rather than taking on fully specified input values, the technique abstractly represents them as symbols, resorting to constraint solvers to construct actual instances that would cause property violations. Symbolic execution has been incubated in dozens of tools developed over the last four decades, leading to major practical breakthroughs in a number of prominent software reliability applications. The goal of this survey is to provide an overview of the main ideas, challenges, and solutions developed in the area, distilling them for a broad audience. The present survey has been accepted for publication at ACM Computing Surveys. If you are considering citing this survey, we would appreciate if you could use the following BibTeX entry: http://goo.gl/Hf5FvcComment: This is the authors pre-print copy. If you are considering citing this survey, we would appreciate if you could use the following BibTeX entry: http://goo.gl/Hf5Fv

Scheduling and partitioning Vlsi circuit operating at multiple supply voltages

With today\u27s increasingly large and complex digital integrated circuit (IC) and system-on-chip designs, power dissipation has emerged as a primary design consideration. Reduction of power consumption in VLSI designs can be achieved at various levels of the design hierarchy, ranging from processing technology, circuit, logic, architectural and algorithmic (behavioral) levels, up to system level. It has also been long recognized that the most dramatic power saving is achievable at the algorithm and architecture levels, where computations are normally described using data/control flow graph. Thus, in this thesis, a multiple supply voltage IC is synthesized at the behavior level; There are, however, a number of practical problems that must be overcome before use of multiple supply voltage becomes prevalent. In particular, lower power is achieved along with an expensive routing cost. Therefore, unlike the existing methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning to reduce power consumption due to the functional units as well as the routing cost; The concerned problem is subsequently referred as the multiple voltage scheduling and partitioning problem (MVSP). The MVSP problem is proved to be NP-complete and three behavioral level synthesis algorithms are proposed to minimize power consumption with resources operating at multiple voltages. One is the polynomial time algorithm. The others are heuristic algorithms, which are tabu search algorithm (TS), and simulated annealing algorithm (SA); In the polynomial time algorithm, synthesis is based on the following three-step process. First, one particular supply voltage (selected from a finite and known number of supply voltage levels) is to be determined for each operation in a data flow graph. Then various operations are scheduled so that the power consumption under given time and/or resource constraints can be minimized. Finally, operations are partitioned into different regions running in different supply voltages to minimize the interconnection costs; In TS and SA algorithms, synthesis schemes are performed to minimize the power consumed by resources and interconnections. In particular, we have configured our solutions with a three-tuple vector to account for both the resource assignment and the partition of operation nodes. Special move operation is designed that allows the scheduling and the partitioning to be performed simultaneously; Experiments with a number of digital signal processing benchmarks show that the proposed algorithms achieve the power reduction at different percentage

Measurements, Models, Systems and Design

531 s.